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Multiple interrupts on MSP430

Other Parts Discussed in Thread: MSP430F5418

I read in the users guide while the MSP430 is in the interrupt service routine then further interrupts are disabled.

What happens if during the ISR anthother interrupt happens?

Does the interrupt get handled when the ISR completes or is it lost?

  • If one interrupt is being serviced and the CPU is executing instructions in that ISR, other pending interrupts wait until the completion of the servicing ISR. Then the next interrupt will be serviced according to its priority in the device datasheet.

  • From the MSP430x5xxx User Guide (SLAU208C):

    Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine. When interrupt nesting is enabled, any interrupt occurring during an interrupt service routine interrupts the routine, regardless of the interrupt priorities.

    Seems it depends on the particular chip as to how it works.

  • I have external interrupt signal in P1.0. In PORT1_ISR I wanna start Timer_A0 to flash the LED connected to P2.1. How should I do???

     

     

  • This seems like a simple thing, I think.

    If you PORT1_ISR is firing based on the external interrupt, just enable your Timer_A0 and the TimerA0_ISR can toggle the LED on P2.1.  Have a flag that also tells you Timer_A0 has been enabled, so that you do not "re-enable" it if PORT1_ISR fires again.

    I think this is one way to do it, for a very simple test or small application.

  • Hi,

    One more additional question,

    Is it possible to use multiple interrupts with Timer,

    say if I am using TACCR1 and TACCR2,

    is it possible to enable TACCR2 interrupt while TACCR1 is in process.

     

    Thankyou in advance.

     

  • A quick question related to LPM0 to 4 . How and when does the device enter into the Low power mode ?

    In the user guides exit from LPM's is clear but entry is not really clear. Please help.

     

  • Hi...

    Regarding interrupt priorities,

    I am using timer A and timer B interrupts. 

    In the timer A ISR, I have a function which takes more time.  I thought that timer B ISR which has higher priority over timer A,

     would pre-empt  timer A ISR and do its high priority work without delay.   

    But, I oberve that timer A ISR gives chance to timer B ISR only after it runs to completion.  Is this the expected behaviour ?  

    Or in general,  Can a higher priority ISR pre-empt lower priority ISR while it is running  on MSP430f5418?

    Thanks.

  • , please start a new thread for your question.

  • Krish,

    Please take a moment to re-read the other answers in this thread.  They are good answers.

    While the GIE bit in the SR is clear, interrupt requests of all priorities remain pending.  The CPU keeps doing whatever it is doing while the interrupt requests wait.

    If the GIE bit in the SR is set, the highest priority interrupt pending is recognized and its ISR begins execution with the GIE bit clear.  Normally, the ISR leaves the GIE bit clear, so normally, the ISR finishes before any other ISR can run, no matter the priority.

    However, an ISR can purposely set the GIE bit to allow another interrupt to be recognized.  Any interrupt (including lower priority interrupts) can then cause the interrupted ISR to wait.

    Most MSP430 users don't allow nested interrupts because ISRs are very small and fast.  If you think you need nested ISRs, consider writing smaller, faster ISRs, leaving most work to the "mainline" code.  If you still think you need nested ISRs, consider using DMA for high-priority, high-bandwidth I/O.

    Jeff

  • Jeff,

    Thanks for the explanation.  

    I had a low priority core function (runs every 50 ms)  in timer A ISR as I thought  it would allow timer B ISR (1ms.. high prio) run intermittantly   throughout.

    Setting GIE bit  doesn't help as my core function inside timer A is large.  

    It will continue to run after resuming execution, this time with GIE bit clear and therefore blocking Timer B.

    So, I will have to reduce timer A core-function and shift it to main.  

    Thanks once again to all for the explanation.

     

  • I think you still have not the right idea on how it works.

    As a quote from the user guide:

    Interrupt Nesting
    Interrupt nesting is enabled if the GIE bit is set inside an interrupt service
    routine. When interrupt nesting is enabled, any interrupt occurring during an
    interrupt service routine will interrupt the routine, regardless of the interrupt
    priorities.

    Now you have most likely set the GIE in your main function to enable the timer interrupts. If an interrupt occurs, the MSP will enter the ISR, if you take a look at the registers now, GIE will be cleared. So if the first thing you do in the ISR is to set the GIE again, you enable interrupt nesting. This should fix your problem.

    Or is it, that you enable GIE in the timer A ISR, it enters timer B ISR and on return the GIE is no longer set? This would be a bug, because the manual states this:

    Return From Interrupt
    1) The SR with all previous settings pops from the stack. All previous settings
    of GIE, CPUOFF, etc. are now in effect, regardless of the settings used
    during the interrupt service routine.
     

  • While this is an older thread, I want to add something important, as it was the cause of trouble in several otehr cases regardign nested interrupts:

    Bernhard Weller said:
    Interrupt Nesting[...]
    If an interrupt occurs, the MSP will enter the ISR, if you take a look at the registers now, GIE will be cleared. So if the first thing you do in the ISR is to set the GIE again, you enable interrupt nesting. This should fix your problem.
    The first thing in an ISR should be clearing the interrupt source. Some (few) interrupts will do so automatically as soon as the ISR is called. This is the case for the Timer CCR0 interrupt vectors. Others are cleared when the actual interrupt reason is fetched by reading the interrupt vector. This is true for e.g. the TAOV and TACCRx interrupts (except TACCR0), while others require manually resetting an IFG bit in a module register, reading the input buffer, writing to the output buffer etc.

    If the interrupt source is not reset, setting GIE will cause the processor to immediately respond to the very same interrupt event again and again, causing an endless loop and finally a stack overflow and system crash.

    The first thing an IST should do is detectign and clearing the cause of an interrupt, then it should save any data that might change if too much time passes, then it may set GIE and do the slower, longer work, being eventually interrupted by a different interrupt.

    It may happen that  the ISR is interrupted by the same interrupt, e.g. if it took too long to write back the received character (due to other interrupts) and then the next data byte arrives and causes the next interrupt.
    This shouldn't happen regularly (else something is seriously wrong with the program design) but if there is a chance that it happens now and then, the ISR should be able to handle it, e.g. by incrementing an offset counter, so the second received byte isn't written before the first received etc.

    A typical case is an ISR that handles a port interrupt which comes in from a bouncing signal. If the ISR enables interrupts for nesting, it may be called several times before the signal settles. Each time being a new interrupt event, but all referring to the same button press. The ISR should be able to handle this by settign a marker, defining timeouts, whatever.

     

    Nested interrupts are a difficult thing full of claws and spikes and should be only used if absolutely necessary.

  • Ah yes, a very good addition and true as well, I haven't used interrupt nesting until now, so I haven't experienced any of the common pitfalls. Thank you.

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