ADC12 configuration for msp430f5xxx series

Ars

I have not used internal ADC12OSC assuming that it requires  a calibration routine and can vary from 4.2 to 5.4 MHz.

Ther eis no 'calibration'. Of course you can determine the exact frequency and take it into account, but for your applicaiton this is not necessary. You provide the start timing for a swequence by a timer, So it doesn't matter whether the sequence takes a few µs more or less. The important thing is the distance between two sequence runs and this is determined by the timer.

Ars

 In a  'sequence of channels" mode shall i first reset ADC12SC bit and then read the ADC12MEMx ?

No. When an individual ADC121MEMx result is available, its corresponding IFG bit is set and you can read the value immediately.
ADC12SC itself is automatically cleared when the sequence is finished. At least when SHP bit is set and you only trigger teh start of the sequence. (if SHP is clear, you directly control the sampling buffer gate with ADC12SC, so you must set and clear it for every single conversion)

Ars

Start the sample & conversion  from timer interrupt routine.

Not the best solution, except if you want to determine inside the ISR whether to start a sequence at all. Using a CCR units output bit (usually TACCR0, TBCCR0 or TBCCR1) can do it at the exact moment of the timer event without need for any software. See ADC12SHSx

Ars

By the time next timer interrupt( 156.25 usec later) comes, adc should  have sampled & converted  and store the result  of all 8 channel in adc buffer.

Why not instead having an ISR triggered by the ADC12 interrupt that is triggered when a specific ADC12IFGx bit is set (usually, the one for the last ADC12MEM in the sequence is used, but for tight timing and to overcome interrupt latency, the forelast step in the sequence can be used to trigger the interrupt, or two of them for first and second half of a sequence)

Ars

    Let’s  say 25 MHz crystal oscillator used and MCLK = 25 MHz and  ADC12CLK source is MCLK.

I do not recommend it. Using MCLK as clock for the ADC12 prevents the MCU from going into LPM.

Ars

And does it mean to say in the above scenario  fADC12CLK  would be 0.45  to 2.7 MHz

No. You use MCLK=25MHz and ADC12DIV_6 (which divides the clock /7 and equals ADC12DIV__7 - note the double underscore) so f_ADC12CLK will be exactly 25/7=3.57MHz.

In this case you'llneed to set REFOUT=1 and provide the required external capacitors. Same for using ADC12OSC. I'm a bit surprised that using ADC12OSC will operate the ADC ina way that it will leave the specified performance range when usign the internal reference. Thsi seems to be a limitation of thsi specific MSP. The 5438A doesn't have this limitation in the datasheet. The 5438 errata sheet, however, lists the 2.7MHz limitation with REFOUT=0.

Well, you can still use REFOUT=0 and ADC12DIV_1 while staying with ADC12OSC. Just keep in mind that you have eight signals, each conversion takes 13+n clock ticks (n depends on ADC12SHTx setting) and the total needs to fit into your timing interval.

Ars

   void Timer interrupt routine(){ // will call it @ 156.25 usec  or  6400 Hz

didn't you say 200Hz? The sequence only needs to be started once every 1/200s for all channels being sampled with 200Hz. Where did you get the 6400Hz from?

Hi   Jens !!

 Thanks .

Jens-Michael Gross

didn't you say 200Hz? The sequence only needs to be started once every 1/200s for all channels being sampled with 200Hz. Where did you get the 6400Hz from?

Yes the frequency of the signal to be measured is between 50 Hz to 200 Hz . And My code  reads the ADC12 buffer  at a rate of 6400Hz ( 156.25  uSec). So the distance between two reading of 8 channel is 156.25 usec at a sys clock of 25 MHz.

Actually I have to run a timer interrupt ( 156.25 usec) for other tasks. So I thought to use it for ADC too. Hence  explicitly started the sample & conversion of adc signal ( by setting ADC12SC bit)  from this routine.

ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_4+ADC12SHT1_4+ADC12REF2_5V+ADC12REFON;

 using ADC in a sequence of channel mode

Hence each adc channel will take 64 + 13 ADC12Clk cycles. So 8 channel will take 8 x  ( 64 + 13 )adc12clk time which is well within my timer interrupt time.

As per my understanding  ADC will finish one sequence of  sample & conversion and sit idle after 8 x  ( 64 + 13 )adc12clk time  and will wait for a rising edge on ADC12SC bit for next sequence and  that I am doing from the timer interrupt routine.

My doubt is that If I do so, still adc12 sampling period will be as per ADC12SHT0_4, ADC12SHT1_4 bits?

What is ADC12MSC bit does? Does it samples multiple time ? then how many samples?

In general how much sample time will be required for <1LSB error?

regards,

Ars

Ars

If I do so, still adc12 sampling period will be as per ADC12SHT0_4, ADC12SHT1_4 bits

If you set the SHP bit, then yes, ADC12SHTyx controls the time the sampling gate is open to charge the sampling capacitor. For each and every sampling procedure.

Ars

What is ADC12MSC bit does? Does it samples multiple time ? then how many samples?

If this bit is set, the ADC12 doesn't require an individual trigger for each conversion in a sequence. Next conversion of a sequence starts as soon as the previous one is done. If this bit is clear, you'll have to trigger each single conversion manually, even if you have a sequence.

Ars

In general how much sample time will be required for <1LSB error?

It depends on your signal impedance. If you have a low-impedance signal source, only minimum sampling time is required. The higher the signal impedance, the higher smapling time is necessary to charge the sampling capacitor. Also, teh input multiplexer acts as a series resistance ( ~1k) to the sampling capacitor, which has some influence too, limiting bandwidth even on low-impedance signal sources.
It is your job to figure out your system configuraiton and calculate the required minimum sampling time.