So I'm starting to use the 5510, I get the MSP430x5xx Family User's Guide SLAU208f, and in 7 places it says "see RISC 16-Bit CPU." I have spent about an hour looking for this term, and the closest I come is a web search saying to look in the Family User's Guide. That's where I started! I did find it the MSP430x1xx Family User's Guide, but not in any of the x5xx Guides. WTF, over.
I think that chapter is now called CPUX: "This chapter describes the extended MSP430X 16-bit RISC CPU (CPUX) with 1-MB memory access, its addressing modes, and instruction set."
RISC stands for Reduced Instruction Set CPU(?) and is a way to name processors with a huge amount of assembly instructions, most of them doing very few amount of work, but powerful when combined.
CISC stands for Complex Instruction Set, an is the opposite approach. Long, complex instructions which perform intensive work :) VAX was CISC and I never understood it.
Bye!
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kazolaRISC stands for Reduced Instruction Set CPU(?) and is a way to name processors with a huge amount of assembly instructions
No!
Reduced means that it has a (relatively) small (ie, "reduced") number of instructions!
But I don't think the OP was after a definition of the generic term - he was looking for the specific reference in the MSP430 documentation
Bob WhiteMSP430x5xx Family User's Guide SLAU208f
You mean this: http://www.ti.com/lit/ug/slau208j/slau208j.pdf
Bob Whitein 7 places it says "see RISC 16-Bit CPU."
You mean these - all in the Glossary:
CPU Central Processing Unit See RISC 16-Bit CPU dst Destination; see RISC 16-Bit CPU PC Program Counter; see RISC 16-Bit CPU SP Stack Pointer; see RISC 16-Bit CPU SR Status Register; see RISC 16-Bit CPU src Source; see RISC 16-Bit CPU TOS Top of stack; see RISC 16-Bit CPU
CPU Central Processing Unit See RISC 16-Bit CPU
dst Destination; see RISC 16-Bit CPU
PC Program Counter; see RISC 16-Bit CPU
SP Stack Pointer; see RISC 16-Bit CPU
SR Status Register; see RISC 16-Bit CPU
src Source; see RISC 16-Bit CPU
TOS Top of stack; see RISC 16-Bit CPU
Yes, that is pretty sloppy!
However, the CPU is documented in Chatpter 6, "CPUX", whcih begins with the words, "This chapter describes the extended MSP430X 16-bit RISC CPU..."
and that chapter does have sections describing the PC (Program Counter), SP (Stack Pointer), and SR (Status Register); and dst, src, TOS are used in the instruction descriptions in that chapter...
Andy NeilReduced means that it has a (relatively) small (ie, "reduced") number of instructions!
So RISC, depending on how it is interpreted, means either that you have few instrucitons (well, the MSP doesn't have that many - 27 different instructions in total for the standard MSP430 core, 12 more for the MSP430X core), even though the combinations of input and output addressing modes and operands sum up to almost 64k different opcodes. But then, the (unquestionable RISC) SPARC processor did have 2^32 different instruciton words :)
Also, the instructions are reduced. There are no loop, div, mul instructions or such. Most instrucitons are simple binary math or jump. One instruciton, one operation. So the MSP is definitely RISC.It does no, however, implement some things usually found on RISC processors such as instruciton pipelining (which it doesn't need nor can implement due to von Neumann architecture), Harvard architecture (whose two different code and data memory buses are rquired for pipelining), nor the single-word instruciton model (which is also needed for teh straight pipelining). But these are just typical implementation details to make up for the low performance of the typical RISC processor instruciton. Which the MSP fulfils by other means like its orthogonal core concept.
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