On a msp430f2272 is it possible to use rs232 and spi at the same time??
How do I in code disable spi ? I use IAR compiler.
Its possible to have both a UART and SPI on a 2272
UCA0 = UART, MCU pins: P3.4, P3.5
UCB0 = SPI, MCU pins: P3.0, P3.1, P3.2, P3.3
But you would need a external chip to take your UART signal to RS232 levels.
When you say you want to disable the SPI what do you mean exactly? Power it down? Release the pins for GPIO?
Release the pins for GPIO
Michael HansenHow do I in code disable spi ? I use IAR compiler.
Not sure what IAR use but it will be something like this:
If you are using UCA0 (P3.0 3.3, 3.4, 3.5):
UCA0CTL1.SWRST = 1; // set UCSWRST bit to disable interrupts from SPI
P3SEL &= ~(bit0 + bit3 + bit4 + bit5); // clear PSEL bits to release pins from SPI module (i.e. put back to GPIO)
// set PxDIR, PxOUT as you need for the released pins
If you are using UCB0: (P3.0, 3.1, 3.2, 3.3):
UCB0CTL1.SWRST = 1; // set UCSWRST bit to disable interrupts from SPI
P3SEL &= ~(bit0 + bit1 + bit2 + bit3); // clear PSEL bits to release pins from SPI module (i.e. put back to GPIO)
Mark GreenUCA0CTL1.SWRST = 1;
UCA0CTL1 |= SWRST; is to be preferred. (or UCA0CTL1&=~SWRST; for clearing the bit).
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Jens-Michael GrossUse of bitfields for hardware registers is deprecated.
Bit puzzled by this one. I thought it was the other way round i.e. use of bit flags is depreciated?
Either way I wouldnt have thought it really mattered since the assembly for:
Reg.bit0 = 1;
comes out the same as
Reg |= 0x01;
Might make for an interesting discussion in another thread maybe?
Mark GreenReg.bit0 = 1;comes out the same asReg |= 0x01;
Reg |= BIT1|BIT2|BIT5; is a single RMW isntruction, while doing the same with a bitfield results in three separate RMW operations. Since Reg is volatile, the compiler is forced to do exactly as many accesses as the code has. And with bitfields, this are three separate ones.
This is why I said it is deprecated, not disallowed. :)
Also, newer header files don't carry the bitfield definitions anymore.
For self-defined bitfields, which are on normal memory and not volatils (not intended to be used inside ISRs), the compiler can perform optimization and group all accesses into one.
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