• Join
  • Sign In with my.TI Login
Texas Instruments
  • Products
  • Applications
  • Tools & Software
  • Support & Community
  • Sample & Buy
  • About TI
Sample & Purchase Cart Sample & Purchase Cart
  • Search
  • Advanced
TI E2E™ Community
  • Support Forums
  • Blogs
  • Groups
  • Videos
  • 简体中文
  • More ...
TI Home » TI E2E Community » Support Forums » Microcontrollers » MSP430™ Microcontrollers » MSP430 Ultra-Low Power 16-bit Microcontroller Forum » MSP430 Timer Interrupt Nesting
Share
MSP430™ Microcontrollers
  • Forum
  • Announcements
  • E2E Wiki
Options
  • Subscribe via RSS
MSP430 Resources
  • MSP430 Product Folder
  • MSP-EXP430G2 - MSP430 LaunchPad Value Line Development kit
  • MSP430 Getting Started Guide
  • MSP430 Microcontroller Projects
  • More Resources >
  • MSP430 Timer Interrupt Nesting

    MSP430 Timer Interrupt Nesting

    This question is answered
    paddu1
    Posted by paddu1
    on Aug 20 2012 13:12 PM
    Expert1195 points

    Hi,

    We are trying to implement Interrupt Nesting with the Timer_A interrupt.

    As you know in case of Timer_A the TACCR1 CCIFG, TACCR2 CCIFG have a single interrupt vector TAIV
    And the manual says "if the TACCR1 and TACCR2 CCIFG flags are set simultaneously first the TACCR1 CCIFG is reset automatically
    After that TACCR2 CCIFG flag will generate another interrupt".

    And regarding the Interrupt Nesting the manual mentions
    "Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine"

    So in our program, we have enabled the Interrupt Nesting (with GIE bit set) inside the
    interrupt service routine of TACCR2 CCIFG & TACCR1 CCIFG so that the program accepts other interrupts also.
    (Timer is in continuous with compare mode)

    Unfortunately the result in our case is, if the TACCR1 and TACCR2 CCIFG flags are set simultaneously
    TACCR1 CCIFG flag is processed but the TACCR2 CCIFG is ignored(canceled),
    but if we remove the Nesting(with GIE bit) then the TACCR2 CCIFG is also processed.

    Please let us know if it is not possible to use Interrupt Nesting in case of TACCR1 CCIFG, TACCR2 CCIFG interrupts?

    Regards.
    Paddu

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    All Replies
    • old_cow_yellow
      Posted by old_cow_yellow
      on Aug 20 2012 13:45 PM
      Guru25715 points

      Interrupt nesting for MSP430 is difficult to do and the benefits may be marginal. Usually there is nothing wrong in handling ISRs quickly and orderly one at a time. If you really want to juggle more than one ISRs, it is like a circus act and you might drop them if you are not skillful.

      Yes, you should be able to handle nested TACCR1 CCIFG and TACCR2 CCIFG interrupts. But why do you want to?

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • Marco
      Posted by Marco
      on Aug 20 2012 14:20 PM
      Expert1420 points

      Hello,

      I just can join the post of old yellow cow (easier than old cow yellow).

      If you want to do interrupt nesting you will lose the main loop (at least on MSP430) . Or in other words you will lose your programs flow.

      Regards

      Marco

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • old_cow_yellow
      Posted by old_cow_yellow
      on Aug 20 2012 21:55 PM
      Guru25715 points

      Marco
      ... If you want to do interrupt nesting you will lose the main loop (at least on MSP430) . Or in other words you will lose your programs flow. ...

      Why is that so? I can see that if you do not do it correctly you will lose the control of the CUP.

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • paddu1
      Posted by paddu1
      on Aug 21 2012 02:51 AM
      Expert1195 points

      Thank you OCY,

      Actually we would like to enable other interrupts also
      while processing TACCR1 CCIFG/TACCR2 CCIFG.

      In case of TACCR0,TACCR1,TACCR2, the interrupt occurs when TACCR0=FFFF
      and then the TAIFG should occur as per the manual,
      but if we enable the Nesting (with GIE bit) the TAIFG seems to be ignored
      after processing TACCR0 CCIFG.

      Below is the part our assembly code.

      TA_HND:
         ADD &TAIV,PC        ;Add offset to the jump table
         RETI
         JMP CCIFG_1_HND ; Vector 2: TACCR1
         JMP CCIFG_2_HND ; Vector 4: TACCR2
         RETI                       ; Vector 6: Reserve
         RETI                       ; Vector 8: Reserve
         JMP TAIFG_HND     ; Vector 10: TAIFG
         RETI
         RETI

      CCIFG_1_HND:           ; Vector 2: TACCR1 Flag
          bis.w #GIE, SR        ; Enable Nesting
           ...
           RETI

      CCIFG_2_HND:           ; Vector 4: TACCR2 Flag
          bis.w #GIE, SR        ; Enable Nesting
           ...
           RETI

      TAIFG_HND:              ;Vector 10: TAIFG Flag
          bis.w #GIE, SR      ;Enable Nesting
          ...
          RETI

      Regards
      Paddu

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • Jens-Michael Gross
      Posted by Jens-Michael Gross
      on Aug 21 2012 09:33 AM
      Guru140085 points

      First a word of warning:

      Interrupt nesting is only for very, very experienced coders. Your ISR needs to be either reentrant or teh code design mus tensure that the same interrupt cannot ever happen before the nesting ISR has finished. This is very difficutl and if not done properly and carefully , it will lead to unexplainable crashes that may even happen first when the product is already in the field.

      If you want to handle all interrupts as fast as possible and want to spare the ISR exit and reentrance time, you can handle them in a loop:

      while(1)
        switch(_even_in_range(TAIV,0x0e){
          case 0: return; // no more interrupts pending, exit ISR here.
          case 2: break; // CCR1 interrupt
          case 4: break; // CCR2 interrupt
          case 6: case 8: case 0x0a: case 0x0c: break; // reseverd for CCR3..6 on larger TIemrA modules
          case 0x0a: break; // timer overflow
        }
      }

      This will handle all pending interrupts in a loop until no more are pending, then exits the ISR



      _____________________________________
      Before posting bug reports or ask for help, do at least quick scan over this article. It applies to any kind of problem reporting. On any forum. And/or look here.
      If you cannot discuss your problem in the public, feel free to start a private conversation: click on my name and then 'start conversation'. But please do so only if you really cannot do it in a public thread, as I usually read all threads. And I prefer to answer where others can profit from it (or contribute to it) too.

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • old_cow_yellow
      Posted by old_cow_yellow
      on Aug 21 2012 14:37 PM
      Verified Answer
      Verified by paddu1
      Guru25715 points

      Paddu,

      The partial code you have shown are okay. But I do not know about the part that you did not show. I wrote a silly demo for the LaunchPad. You may want to take a look. 0508.Nest_ISR.txt

      I slow down the clocks and use the two LEDs on the board to show what is going on. The main loop turns on both LEDs dimly. The Timer is set up to generate 3 different interrupts almost at the same time every 5 seconds or so.  The interrupt handlers blink the LED brightly in three different ways.

      This demo works as expected. If you turn on the nesting, it still works. The only difference is that the priorities are inverted and the stack is deeper.

      When interrupts are not nested, you see Green, Red, then Green+Red every 5 seconds or so. The stack is 10 bytes deep.

      When interrupts are nested, you see Green+Red, Red, then Green every 5 seconds or so. The stack is 22 bytes deep.

      -- OCY

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    • paddu1
      Posted by paddu1
      on Aug 22 2012 03:03 AM
      Expert1195 points

      Thank you very much.

      Report Abuse
      • Reply
      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
    TI E2E™ Community
    • Support Forums
    • Blogs
    • Videos
    • Groups
    • Site Support & Feedback
    • Settings
    TI E2E™ Community Groups
    • TI University Program
    • Make the Switch
    • Microcontroller Projects
    • Motor Drive & Control
    Other Communities
    • Deyisupport
    • Designsomething.org
    • beagleboard.org
    • TI on Element 14
    • TI on TechXchangeSM
    Other Technical & Support Resources
    • WEBENCH® Design Center
    • Product Information Centers
    • Technical Documents
    • TI Design Network
    • TI Technical Articles
    • TI Training

    All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

    Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site. TI, its suppliers and providers of content reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

    Follow Us Texas Instruments on Facebook Texas Instruments on Twitter Texas Instruments on LinkedIn Texas Instruments on Google+
    TI Worldwide | Contact Us | my.TI Login | Site Map | Corporate Citizenship | mobile m.ti.com (Mobile Version)

    TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs and
    embedded processors, along with software, tools and the industry’s largest sales/support staff.

    © Copyright 1995-2013 Texas Instruments Incorporated. All rights reserved.
    Trademarks | Privacy Policy | Terms of Use