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MSP430 Ultra-Low Power 16-bit Microcontroller Forum
Timer_A capture Compare register
Hi everybody, marry Christmas and a huppy new year,
Using the examples described within slac015 for practice and more specifically the example ta_10 (MSP-FET430P140 Demo - Timer_A, Toggle P1.1/TA0, Up Mode, DCO SMCLK), could you please inform me what is the meaning of the following:
CCR0 is loaded with 500-1and TA0 will toggle P1.1 at TACLK/500.
Having in mind how Timer_A works iam understanding that Timer gets an input signal as reference frequency which must be capture-compared with the set frequency signal of Timer_A at a specified edge.
500-1 devides the frequency of TACLK ? and if does for what reason, maybe to set when the capture must be performed?
Kindly looking for your help.
It would be helpful for you to review the Timer_A section, Chapter 11, of the MSP430x1xx User's Guide (SLAU049) to provide a description of how the Timer_A is setup in the code example of fet140_ta_10.c.
In this code example, the Timer_A is configured for Up Mode (described on page 11-6) whereby the timer repeatedly counts up to the value of the compare register TACCR0, which defines the period. The TASSELx bit field in the TACTL register controls which source reference clock is provided to the Timer_A, which in this particular case is SMCLK. In Figure 11-1, you can see the block diagram of the Timer_A. You will see that the TAR counter is clocked from one of 4 sources, including SMCLK, which is controlled by the TASSELx bits and further is possibly divided by the IDx bit field. This is the clock for the counter TAR. When TAR = TACCR0, in this particular case, the counter will behave as illustrated in Figure 11-2 where the TAR will then reset to 0h and start counting up again.
On these compare events, you can set the behavior of the Timer_A output on P1.1. This is defined in the CCTL0 register with OUTMOD_4. Output Modes are described in Table 11-2 and OUTMODE_4 toggles the specified output, which in this case is the output of TACCR0 on P1.1. In essence, the output on P1.1 is double the timer period (aka. TACCR0).
That comment is the result of many things.
In "Up Mode", TAR counts the TACLK up to the value in CCR0 and resets to 0. Thus it repeats itself every (CCR0+1) clocks.
TACCTL0 is set to toggle OUT every time CCR0 matches TAR. Thus OUT toggles every (CCR0+1) clocks as well.
P1DIR.1 and P1SEL.1 are both set. Thus the OUT from CCR0 appears at P1.1
You need to read the Users Guide. Without that, it is difficult to understand how it works.
Thank you very much for your help,
Due to the fact that am reading allown, some times i make my self confused for thiings which maybe simple, as i have already read this chapter of manual.
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