• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 79 subscribers
  • Views 1553 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TimerA vector0 interrupt enable

ravanee
Prodigy 20 points
Other Parts Discussed in Thread: MSP430F5529

MSP430: MSP430F5529 Launchpad

IDE: IAR Embedded Workbench

I am trying to setup a periodic tick at 1ms. My code setups TimerA in up mode, CCR0 counting 0 to 999, with an SMCLK at 4MHz divided by 4 resulting in a 1MHz input clock. Before I leave my initialize function, I set TAIE in TA0CTL to (what I thought would) enable the interrupt for TimerA vector0. However, this seems to have the opposite effect and I don't break inside my TIMER0_A0_VECTOR ISR. When I leave out the interrupt enable line, interrupts are being generated. I can't find much information in the family user guide about this (looking at slau208m). Is this correct?

Here is my code:

#define SYSTEM_TIMER_us     (1000) 

///// Hardware /////
// TASSEL_2 : SMCLK (4MHz)
// ID_2 : Divide input clock (SMCLK) by 4 (resulting in 1MHZ)
// MC_1 : Put in up mode to CCRO
TA0CTL = TASSEL_2 + MC_1 + ID_2;
// Set CCR0 to expire every 1ms
TA0CCR0 = SYSTEM_TIMER_us - 1;
// Clear CCR0 interrupt flag
TA0CCTL0 &= ~CCIFG;
// Allow interrupt
TA0CCTL0 |= CCIE;     

// Clear any pending flags
TA0CTL &= ~TAIFG;
// Enable  TimerA interrupts
TA0CTL |= TAIE;                //<<<<Line in question

  • 0
    Guru 16361 points

    Section 17.2.6 of the user guide covers this. TimerA has two interrupt vectors. TIMER0_A0_VECTOR handles TA0CCR0 CCIFG, while TIMER0_A1_VECTOR handles all other interrupt sources on TA0 (including TAIFG).

    TAIE isn't a module-global "enable all interrupts" flag, it enables the TAIFG interrupt which fires when TAR counts to zero. In up mode that happens one timer tick after TAR counts to CCR0. 

    To handle the CCIFG interrupt for TA0CCR0 you just need to set CCIE in TA0CTL0 and enable interrupts globally by setting GIE.

  • 0
    Genius 4140 points

    Hey Ravanee,

    Timers are simple yet complex modules in in MSP430 MCU (subjective tough :) ) .  You will get around with this once you gain experience in working around with timers. For time being, Timer A in Msp430F2xxx series has 2 types of interrupts, 
    1.  Capture/compare interrupts
          a. TA1CRO --- FALL UNDER "TIMER1_A0_VECTOR"
          b. TA1CCR1 
               TA1CCR2 UNDER TIMER1_A1_VECTOR

    2. timer overflow interrupt
          a. TAIFG  again under TIMER1_A1_VECTOR

    All you have to do, is to have an Idea of what you are using and what you want., You have to set those corresponding interrupt flags that you are intending to work with.

  • 0
    Guru 227245 points

    TIMER0_A0_VECTOR is for the interrupt of the capture compare unit 0 (CCR0). It is enabled by setting CCIE in TA0CCTL0.
    For TAIE (and all other CCRx units), TIMER0_A1_VECTOR is to be used.

    It's also very important that you manually clear the IFG bit that triggered the interrupt before leaving the TIMER0_A1_VECTOR ISR. Or else it will be called imediately again and again. (TAxCCR0.CCIFG will be automatically clear when TIMERx_A0_VECTOR ISR is entered)

  • 0
    Prodigy 20 points

    Thank you all for the replies. I now understand that Timer0_A0_vector is tied to TA0CCTL0. But why would enabling interrupts in TA0CTL (for CCRs > 0) keep me from generating interrupts for the A0_vector? Can I not have interrupts enabled for CCR0 and CCR1 at the same time?

  • 0 in reply to ravanee
    Guru 16361 points

    ravanee said:

    Thank you all for the replies. I now understand that Timer0_A0_vector is tied to TA0CCTL0. But why would enabling interrupts in TA0CTL (for CCRs > 0) keep me from generating interrupts for the A0_vector? Can I not have interrupts enabled for CCR0 and CCR1 at the same time?

    Yes, you can use both together, but you must then implement both TIMER0_A0_VECTOR and TIMER0_A1_VECTOR. Otherwise you'd be forcing the MCU to call an ISR that doesn't exist, which is bad news (IIRC it causes a jump to address 0x0000).
  • 0 in reply to ravanee
    Guru 227245 points

    It won’t keep you from using other interrupts, but for all you enable you need to provide the proper ISR. If you use CCR0.CCIE, then you need the TIMER0_A0 ISR. For any other TA0 interrupt, you need the TIMER0_A1 ISR.
    Also, TAIE in TACCTL does enable the timer overflow interrupt that happens when TA0R rolls over to 0. It is independent of the CCRx.CCIE interrupts and not a global ‘enable TimerA interrupts’ bit.

    Robert, actually it is a jump to 0xFFFE (the vector contains 0cFFFF, but the LSB is ignored for PC register) However, the next instruction after whatever the reset vector may look like when interpreted as an instruction, will be fetched from 0x0000 or 0x0002. And an instruction fetch from the special function register area will cause a PUC.

**Attention** This is a public forum