Can the MSP430 I2C Master be forced to complete a write sequence when the I2C slave NACKs the address cycle?

No. If no ACK is detected, the master won’t continue but rather wait for you to send a stop. Without slave, it is futile to continue.
I agree that for debugging, it could be useful, but the only way for a transmission is to have a slave that sends an ACK.

Well,

i think this is not possible when using USCI/eUSCI module, but i think it should be possible when using USI module - CMIIMW. So the question is: which device are you referring to?

I am using the MSP430F5529 which has USCI and eUSCI.

Leo, you’re right. The USI is not much more than a software-controlled shift register with baudrate generator, so interpretation of the received ACK signal is left to software. Yes, the USI can do almost everything (but can do nothing conveniently). It can even be used for hardware-clocked UART TX J

 Randy, none of the MSPs has both, USCI and eUSCI. The older 5x family devices have an USCI while the newer ones have an eUSCI as a more advanced version. But none has both types.
In the 2x and 4x family, however, there are some devices that have an USI and an USCI or an USCI and an USART.

JMG,

Jens-Michael Gross said:

Leo, you’re right. The USI is not much more than a software-controlled shift register with baudrate generator, so interpretation of the received ACK signal is left to software. Yes, the USI can do almost everything (but can do nothing conveniently). It can even be used for hardware-clocked UART TX J

Well theoritically it is possible to use it as UART TX, but the there is no flexible baud rate divider setting in USI module for getting the standard UART baud rate (e.g. 9600 etc), you can only divide the clock with the power 2 divisions using USIDIVx bits of USICKCTL. This would require the user to use external clock matching the standard baud rate, e.g. 1,8432 MHz with 57600/115200 baud.

True, the baudrate control of the USI isn’t the most flexible.
But that’s not worse than on the Atmel. The “Ethernut” module (based on ATMega128) uses a 14.7456Mhz crystal for the CPU because of it being a multiple of 115200. The ATMega UART has the same limitation as the USI.
It seems to be a quite common crystal frequency, so apparently other MCUs are as 'unflexible' too.