MSP430G2955: Timer behavior

Before proceeding, I must say that my answer is not authoritative, and I haven’t ever really tested these cases myself. But from what I read in the users guides and errata sheets. So the answers below refer to the intended/described behavior…

Case A:  yes, the CCR2 interrupt will happen. The timer counts to CCR2, no matter how it got to (CCR2-1), so this triggers the interrupt.

Case B: The overflow interrupt won’t happen. The timer has not counted to 0. It was set to 0 (and can be immediately read as 0) before it counted to 0 (and therefore technically never has overflown). So no overflow interrupt will happen. But on the next rising edge, it will count to 1 (so your drawn timing of TA0R==0 is too long by one clock cycle). CCR2 interrupt will happen on the rising edge immediately following the clear.

Case C: Again, the overflow interrupt won’t happen, as the timer never counted to 0. And yes, it will count on the rising edge and cause a CCR2 interrupt.
Things will get more complicated if you use the prescaler. Clearing TAR will also clear the prescaler. But since is it a down-counter, the next clock edge will cause the timer to count up. So in summary, after a clear, the timer will always count on the next rising edge.

Jens,

Thank you for you response.

I revised my power point documents which I had posted.

Would you please point out the correct pattern in each cases?

3755.20140417_Timer_clear_timing.pptx

And please let me confirm the following question.

[Question]

If read the Timer count(TA0R) value, is the value which I had written in PPTX file correct?

Please check my power point which I attached in above.

If you have any questions, please let me know.

Best regards.

Kaka

Hi community member,

Please let me confirm the following question in addition to above my post.

[Question]

Would you please point out the correct pattern in each cases which is written in the attached PPTX file as below?

2577.20140418_Timer_clear_timing.pptx

And I woud like to know whether the CCRx interrupt will be happen in those cases.

So, please provide your comments to us for this point of view.

If you have any question, please let me know.

Best regards.

Kaka

I can't open ppt right now, so the following (pre-recorded) answer refers to the second version of your presentation, not the last:

In case A, pattern 1 is correct.

In case B, pattern 1 too. However, on some MSPs, you’ll get a (bogus) overflow interrupt simultaneously with CCR2 interrupt when the counter counts to 1 (that means: at the next rising edge after the counter was set to 0). This is a documented erratum (and also happens if you stopped the timer before clearing it)

In case C, again pattern 1 is right. And again, on some MSPs, the above erratum applies.

 So as a general workaround don’t reset the timer while it is running. And on affected devices, check before clearing it whether the current count was one tick before overflow. If so, take care for this bogus overflow interrupt. E.g. by disabling the overflow interrupt and waiting until the counter has reached 1. Or by signaling the ISR to ignore the next overflow interrupt. Well, the first won’t do any harm even on devices where the erratum doesn’t apply.