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I2C problems with SDA and SCL line

Other Parts Discussed in Thread: MSP430F5659

I have been working on some code to communicate with an NFC chip (PN532) from my MSP430F5659 for a while now and the code works great.  we recently got our main bored in so its time to move from the development bored to the main bored.  however even with the same value of pull up resistors and everything being exactly the same im having erratic behavior on both the SDA and SDL lines.  im running the exact same code with nothing else added to the code for anything else on the board.  nothing else is on the sda and sdl line at the moment. iv checked and rechecked  and everything should be fine but on rising edges it gets screwed up.  any thoughts?

      

  • In reality, there are no true digital signals (except for sub-atomic affects). All signals are transmitted by analog media. If you look at your scope shots, you see that the signal doesn’t show rectangles. This is because the signal is influenced by things like line impedance or parasitic capacitance. The falling edges (caused by the device driver) are steep, but the rising ones are not. As you can see, the short signal spikes don’t even have enough time to rise to maximum voltage before they are pulled low again. So you need to lower the pull-up resistor. On your development board, the signal form might have been still sufficient to be properly recognized by the other side, but on your new main board, traces and therefore impedance and capacitance are different and this may have crossed the border. Or variations in the chips used have changed the reception levels.


    Your logic analyzer, while being a useful tool, is interpreting the signals again in a different manner (regarding at which voltage the signal is considered to be high or low)

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