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MSP430F5xx code execution question

Daniel Wang1
Prodigy 20 points

I'm new to MSP430F5xx. When I am porting a project from STM32L to MSP430F5xx, I find that some codes are compiled into 2-byte command and 4-byte command. I wonder if 4-byte commands can be interrupted. When using FET debugger to step in the code, it seems one step in can process this 4-byte command. Is there anybody who knows the behavior of MSP430F5 for these 4-byte command? Thanks in advance.

Example, .s file:

Source code:                          bReceived = FALSE;

4-byte command:   009ADC    4382 2ADA             clr.w      &bReceived

Source code:                          RecvState = RECV_IDLE;

4-byte command:  009AE0      43C2 268D             clr.w      &RecvState

  • 0
    Guru 16361 points

    Daniel Wang1 said:

    Source code:                          bReceived = FALSE;

    4-byte command:   009ADC    4382 2ADA             clr.w      &bReceived

    Source code:                          RecvState = RECV_IDLE;

    4-byte command:  009AE0      43C2 268D             clr.w      &RecvState

    In those examples the first word is the opcode and the second is the destination address. Each clr instruction will complete atomically, and won't be interrupted part-way through.

    For detailed information on the instruction set, including addressing modes and opcode format, see chapter 6 of the MSP430x5xx and MSP430x6xx Family User's Guide.

    Section 1.3.4.1 of the guide gives an explanation of the interrupt acceptance procedure. The relevant point there is step 1: "Any currently executing instruction is completed."

    Finally, it's a good idea to check the MSP430F5529 Device Erratasheet for CPU errata. Usually the compiler will work around these (if possible), but they're worth knowing about anyway.

  • 0 in reply to Robert Cowsill
    Prodigy 20 points

    Thank you for your help, Robert. I think you are right.

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