Hello All,
In lab 3 there is a section of code that stops the DCO.
_bis_SR_register(SCG1 + SCG0);
In looking at the header file the values of SCG1 and SCG0 are
#define SCG0 (0x0040)
#define SCG1 (0x0080)
The result of the command will then set the SR registers so that bits 6 and 7 are enabled.
In the DCO section it indicates to disable the DCO you:
Software can disable DCOCLK by setting SCG0 when it is not used to source SMCLK or MCLK in active
In the SR Bit table:
SCG1 System clock generator 1. This bit may be to enable/disable functions in the clock system depending on the device
family; for example, DCO bias enable/disable
SCG0 System clock generator 0. This bit may be used to enable/disable functions in the clock system depending on the
device family; for example, FLL disable/enable
my question is, I can see why we set SCO to enable to disable the DCO,
But what is SCG1 doing, not sure what DCO bias is doing.
Any assistance would be appreciated.
Thanks
Joe
