not able to display ADC(8 BIT) values for 12 Mhz clock for msp430f5438a controller

hi,

we are trying to run ADC(8 bit) for msp430f5438a at 11278hz at a clock of 12Mhz.the input to ADC is sine wave function generator.when we trying to plot the graph using python programming or check the values on the hyperterminal no values are coming.the baud rate is set for 115200

i am pasting the code.please check whether it is correct or wrong.what changes i have to make?

#include "msp430f5438A.h"
#include<stdio.h>
#include<string.h>
#include <stdint.h>

char buffer[100];
static uint8_t SavedADC12MEM1; //To store ADC outputs

void SetVcoreUp (unsigned int level);
void accelerometerInit(void);

int main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
SetVcoreUp (PMMCOREV_1); // Set VCore = 1.6V for 12MHz clock
//P1DIR |= BIT0; // P1.0 output
// P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
// P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
UCSCTL4 = SELS__DCOCLKDIV ;

UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
//UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);

// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag

accelerometerInit();
while(1)
{


ADC12CTL0 |= ADC12SC;
__bis_SR_register(LPM0_bits+GIE); // Enter LPM0, enable interrupts
__no_operation();

// For debugger
//adcStartRead();

// TA1CCTL0 = CCIE; // CCR0 interrupt enabled
//TA1CCR0 = 212;

//TA1CTL = TASSEL__SMCLK + MC__UP + TACLR; // SMCLK, up mode, clear TAR

// initialize USCI module
P5SEL |= BIT6 + BIT7; // P5.6,7 = USCI_A1 TXD/RXD
UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
UCA1CTL1 |= UCSSEL__SMCLK;
UCA1BR0 =104; //
UCA1BR1 = 0; //

UCA1MCTL = UCBRS_1;

UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**

int k=0;




sprintf(buffer,"%d ",(SavedADC12MEM1));

while(buffer[k])
{
while(!(UCA1IFG&UCTXIFG)); // USART0 TX buffer ready?
UCA1TXBUF = buffer[k++];
}

//UART_outdec(SavedADC12MEM1, 0);
}
}

void SetVcoreUp (unsigned int level)
{
// Open PMM registers for write
PMMCTL0_H = PMMPW_H;
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}

void accelerometerInit(void)
{
P7SEL |= BIT5; // Pin 7.6 and 7.7 are inputs from the accelerometer to the ADC => they are configured as inputs to the ADC
P7DIR &= ~BIT5;

// UCSCTL8 |= SMCLKREQEN ; // ADC is clocked by the ACLK in the UCS module


//REFCTL0 |= REFMSTR+REFVSEL_2+REFON+REFTCOFF;
ADC12CTL0 &= ~ADC12ENC; // Disable conversion
ADC12CTL0 = ADC12ON + ADC12SHT0_8 + ADC12MSC ; // Turn on ADC, Sample once every 256 cycles, Multisample conversion
ADC12CTL1 = ADC12CSTARTADD_1+ ADC12SHP + ADC12CONSEQ_0 + ADC12SSEL_3 + ADC12DIV_3;//11278hz
ADC12CTL2 = ADC12RES_0; // Resolution=08 bits, 13 clock cycle conversion time

ADC12MCTL1 = ADC12INCH_13;
ADC12CTL0 |= ADC12ENC; //| ADC12SC;

//select channel 13(pin 7.5)

ADC12IE = BIT1;

__delay_cycles(100); // Allowing reference voltage to stabilize
}