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Reduce sample frequency on MSP430G2553

Armando Ferreira
Expert 1925 points
Other Parts Discussed in Thread: MSP430G2553

How can I reduce the sample frequency y in MSP430G2553 from 200KHz to near 500Hz?

  • 0
    Guru 227245 points

    There are multiple ways. You may lower the ADC clock. (keep an eye on minimum limit). You may raise the sample&hold time.
    You may use a timer and start each conversion individually from the timer ISR. Or you may trigger the start of each conversion using a timer CCR unit. See the ADC chapter in the users guide.

  • 0 in reply to Jens-Michael Gross
    Expert 1925 points

    Jens-Michael Gross,

    Can you show me an example,  I'm new in these technologies and any help is necessary, and it is a great help.

  • 0 in reply to Armando Ferreira
    Guru 227245 points

    There are several other threads in which ADC triggering by timer is discussed. Some with code.

    If you use the S&H timing, the maximum S&H time on G2 series ADC10 is 64 clock cycles. And another 13 clock cycles for the conversion. So 77*500 would be 38500Hz ADC clock. This could be done with an external 32768Hz crystal. However, the ADC10 requires a minimum clock of 450kHz, so this is not an option. (on 5x family ADC10, up to 1024 S&H clock cycles are possible, there it would work)

    So the only option remaining is to use the timer.
    You need to pick a suitable clock speed for the TimerA0. Let’s say 1MHz. Then run the timer in up mode and set the required cycle time (500Hz) with the CCR0 register. 500Hz = 0.002s = 2000 clock cycles@1MHz, so set TA0CCR0 to 1999. Next set the output mode (OUTMOD) to set/reset. Finally, select TimerA0.OUT0 (SHS_2) as trigger source for the ADC. On each timer cycle, it will trigger one conversion.

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