Hi all,
I try to use USI on a MSP430G2452, with CCS 6.0.1.00040 and grace 3.0.1.59. I need to configure an uart at 2kBits/s, transmitting 20 octets packets.
When i try to initialize USI, some fields are locked, whenever i use an old (CCS5) project of mine or an imported example project.
any idea to get over this?
I finally managed to configure the USI using my own initialisation procedure, derived from Grace config files. But using Grace would be a plus.
Here is the code i used. I first set up clock at 2MHz, then timer as clock source for transmission, then USI.
/********************************************** CLOCK * Basic Clock System Control 2 * * SELM_0 -- DCOCLK * DIVM_0 -- Divide by 1 * ~SELS -- DCOCLK * DIVS_3 -- Divide by 8 * ~DCOR -- DCO uses internal resistor * * Note: ~<BIT> indicates that <BIT> has value zero */ BCSCTL2 = SELM_0 | DIVM_0 | DIVS_3; if (CALBC1_16MHZ != 0xFF) { /* Adjust this accordingly to your VCC rise time */ __delay_cycles(100000); /* Follow recommended flow. First, clear all DCOx and MODx bits. Then * apply new RSELx values. Finally, apply new DCOx and MODx bit values. */ DCOCTL = 0x00; BCSCTL1 = CALBC1_16MHZ; /* Set DCO to 16MHz */ DCOCTL = CALDCO_16MHZ; } /* * Basic Clock System Control 1 * * XT2OFF -- Disable XT2CLK * ~XTS -- Low Frequency * DIVA_0 -- Divide by 1 * * Note: ~XTS indicates that XTS has value zero */ BCSCTL1 |= XT2OFF | DIVA_0; /* * Basic Clock System Control 3 * * XT2S_0 -- 0.4 - 1 MHz * LFXT1S_0 -- If XTS = 0, XT1 = 32768kHz Crystal ; If XTS = 1, XT1 = 0.4 - 1-MHz crystal or resonator * XCAP_1 -- ~6 pF */ BCSCTL3 = XT2S_0 | LFXT1S_0 | XCAP_1; /************************************************** Timer A * TA0CCTL0, Capture/Compare Control Register 0 * * CM_0 -- No Capture * CCIS_0 -- CCIxA * ~SCS -- Asynchronous Capture * ~SCCI -- Latched capture signal (read) * ~CAP -- Compare mode * OUTMOD_4 -- PWM output mode: 4 - Toggle * * Note: ~<BIT> indicates that <BIT> has value zero */ TA0CCTL0 = CM_0 | CCIS_0 | OUTMOD_4; /* * TA0CCTL1, Capture/Compare Control Register 1 * * CM_0 -- No Capture * CCIS_0 -- CCIxA * ~SCS -- Asynchronous Capture * ~SCCI -- Latched capture signal (read) * ~CAP -- Compare mode * OUTMOD_4 -- PWM output mode: 4 - Toggle * * Note: ~<BIT> indicates that <BIT> has value zero */ TA0CCTL1 = CM_0 | CCIS_0 | OUTMOD_4; /* TA0CCR0, Timer_A Capture/Compare Register 0 */ TA0CCR0 = 249; /* TA0CCR1, Timer_A Capture/Compare Register 1 */ TA0CCR1 = 249; /* * TA0CTL, Timer_A3 Control Register * * TASSEL_2 -- SMCLK * ID_0 -- Divider - /1 * MC_1 -- Up Mode */ TA0CTL = TASSEL_2 | ID_0 | MC_1; /************************************************* USI /* Disable USI */ USICTL0 |= USISWRST; /* * USI Control Register 0 * * ~USIPE7 -- USI function disabled * USIPE6 -- USI function enabled * ~USIPE5 -- USI function disabled * ~USILSB -- MSB first * USIMST -- Master mode * ~USIGE -- Output latch enable depends on shift clock * USIOE -- Output enabled * USISWRST -- USI logic held in reset state * * Note: ~<BIT> indicates that <BIT> has value zero */ USICTL0 = USIPE6 | USIMST | USIOE | USISWRST; /* * USI Clock Control Register * * USIDIV_0 -- Divide by 1 * USISSEL_5 -- TACCR0 * ~USICKPL -- Inactive state is low * ~USISWCLK -- Input clock is low * * Note: ~<BIT> indicates that <BIT> has value zero */ USICKCTL = USIDIV_0 | USISSEL_5; /* Enable USI */ USICTL0 &= ~USISWRST;