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32.768kHz crystal outputting 8.66kHz for CLKs

Other Parts Discussed in Thread: MSP430FR5739

Hello all,

I'm having some problems with the MSP430FR5739 and using a 32.768k crystal.

I've been using the UART fine with the DCO set at 8MHz, divided down to 1Mhz, for the past few days, and as my project has to be low power and have an RTC, so I decided to install a 32k crystal as the chip supports it and the built in RTC on the chip requires it. I set up the XT1 as directed in the datasheet, and initialsed the UART with the values provided, however I was only getting garbage over the port. As a last ditch, I scoped out the crystal which was giving the correct frequncy and set up some pins of the chip to output the MCLK, SMCLK and ACLK. The clock signals were giving out 8.666kHz according to my scope, which is quite obviously wrong.

Heres my setup code:

    PJSEL0 |= XIN;

    PJDIR |= BIT1 + BIT2 +BIT3;      //Set up pins J.1,2 and 3 to output clock signals

    PJSEL0 |= BIT1 + BIT2 + BIT3;

//CLOCK SETUP

    CSCTL0_H = 0xA5;//Password write to change clock registers

    CSCTL2 = SELA_0 + SELS_0 + SELM_0; //Sets all clocks to XT1 speed

    CSCTL3 = DIVA_0 + DIVS_0 + DIVM_0; //Sets divisor of 0 for all CLKs

    CSCTL0_H = 0x00; //Lock clock registers

I temporaily changed all my clocks back to the DCO and measured the frequencies at the clock pins and they were all as expected. Does anyone have any explanation as to what is causing this problem?

 

  • 8.66kHz likely is the VLO frequency on your MSP (5-13kHz).
    It looks like you are not properly initializing the crystal.

    From the users guide:

    “If XT1 in LF mode is sourcing any system clock (ACLK, MCLK, or SMCLK), and a fault is detected, the system clock is automatically switched to the VLO for its clock source (VLOCLK). Similarly, if XT1 in HF mode is sourcing any system clock and a fault is detected, the system clock is automatically switched to MODOSC for its clock source (MODCLK).”

    So after selecting LFXT1 as clock source, you should see VLO frequency until the fault flags are clear.

    Do you follow the procedure to clear the fault flags? On power-on, the fault flags are set and need to be cleared once the crystal is running.

    Do you clear XT1OFF in CSCTL4? I’m not sure what happens if XT1 has a fault set (which it has right from the start) and the clocks are actually in fallback mode (so not sourced by XT1). The docs are a bit ambiguous here.

  • Thanks very much Jens,

    After posting originally, I did find in the datasheet all the error registers, and checked them, which showed the flags were being set. I replaced the crystal and was still seeing the flags set, but didn't realise that I had to manually clear them. I installed this code at the beginning of my program, before the UART setup and it is now working. Thanks very much!

    while(SFRIFG1 & OFIFG)

        {

             SFRIFG1 &= ~OFIFG;

             CSCTL5 &= ~XT1OFFG;

             CSCTL4 &= ~XT1OFF;

        }

     

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