Howdy All,
I've been writing some code using a semi-unique feature of the FRAM MSPs I2C bus in slave mode, the ability to interrupt on any (and all) 7bit device IDs. I cannot go into details as to what the product is or does (for NDA reasons). I can say that I'm trying to mimic the behavior of some now obsolete EEPROMs that were not 100% I2C compliant (the bus timing is I2C compliant, but they did not have a device ID)
My code works perfectly when used using I2C tools like an aardvark or when controlled by some of my own code written on another MSP. However, when it is attached to the product it was designed to work with, it fails. The problem is that the device it is being attached to is somewhat ill behaved and doesn't completely conform to the I2C standard itself, and I cannot change the behavior of this product.
When the product is first turned on, it searches for this now obsolete EEPROM by polling the bus and looking for something to ACK it, which my code does. The product then sends what appears to be garbage, followed by 9 perfectly valid start conditions followed by what should be STOP. Even though these are actually valid START conditions (and at a relatively slow rate too), I believe that the MSP only sees the first 1, and thinks the others are actually the device ID being clocked in, and the last pulse it is actually sending an ACK (the MSP holds the line low I can only assume waiting for the master to send the next clock)
I've somewhat verified this by sticking some debug code in to count the number of starts and stops received. In this particular instance it claims to have received only 1 start, even though several were sent sequentially. I don't see anything mentioned in the errata about anything like this, but all I can think of is that this MSP doesn't support repeated start under these instances. The data sheet is a bit vague about the min timing as it does say anything about master vs slave mode. If the min timing is truly 4us, then I'm violating that as the start timing I have is around 3.6us, but why then does the aardvark work with sub 1us timing difference between the falling edges of SDA & SCL? I have a few screen shots of my logic analyzer I can upload, but it appears that you can only upload 1 at a time? so hopefully I can upload the other in a follow up shortly.
The picture attached here shows the garbage followed by the 9 start pulses, and the MSP holding the SDA line low.