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MSP430 - FLL

Somnath Pradhan
Prodigy 70 points

What is FLL in MSp 430 need details.... How it works and what is the hardware for FLL. How it is different from PLL. 

  • 0 in reply to Ilmars
    Prodigy 70 points

    Details Needed... from the ... The all known!!!!

  • 0 in reply to Somnath Pradhan
    Guru 46710 points

    Somnath Pradhan said:
    Details Needed

    What kind of details. "Tell me how FLL and PLL works?"  - well, information is all over the internet. Use internet search engines and you will get the details.

  • 0 in reply to Ilmars
    Prodigy 70 points

    FLL...........How it works.. how to design one.... will it work like PLL. No tutorial needed about PLL. It well understood.

    Is it possible to implement FLL in DSP.

  • 0 in reply to Somnath Pradhan
    Prodigy 70 points

    I am unable to find more details about FLL. can you please send me some link on FLL (detailed info - not one paragraph.)I do not need any more information or tutorial About PLL.

  • 0 in reply to Somnath Pradhan
    Guru 46710 points

    Somnath Pradhan said:
    No tutorial needed about PLL

    Very good. FLL measures frequency error (higher/lower freq), PLL measures phase error (ahead/behind phase). The remaining parts of both are more or less equal - error signal is used to steer VCO (voltage controlled oscillator) or DCO (digitally controlled oscillator).

    Somnath Pradhan said:
    Is it possible to implement FLL in DSP.

    Indeed. You measure both - oscillator frequency and reference frequency, compare them. Then passing error signal through loop filter steer your oscillator ( VCO or DCO or even DDS ).

    Possibly not the best articles, but at least I did what you asked: used google for you.

    https://www.eecis.udel.edu/~mills/ntp/html/discipline.html

    http://www.semtech.com/images/datasheet/xe8000_tn_09_locked_loop.pdf

  • 0 in reply to Ilmars
    Prodigy 70 points

    seems to be information..... i have found some iEEE paper on this http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=938354&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F82%2F20317%2F00938354.pdf%3Farnumber%3D938354

    hope this will help

  • 0
    Guru 227245 points

    Basically, an FLL compares two frequencies by counting the clock pulses of the target frequency during one clock pulse of the reference frequency, and comparing the count with the given factor. Then it raises or lowers the target frequency in fixed steps. For a long-time average, this is fine. And doesn’t require much energy (after all, it is just two counters and a compare). But it limits the possible target frequencies to an integer multiple of the reference.
    The reference clock can be very low, which reduces the power required for a low-frequency crystal, with a high factor. (you can get 25MHz from a 32kHz reference). In fact, the higher the factor, the better the result (less long-time jitter due to constant corections). FLL fails if the factor is too low, and for best results it should be >32 due to the 32 modulation steps in the DCO.

    A PLL requires a lot of power, as it compares the phase of the target frequency and the phase of the source frequency, based on multipliers and dividers. When locked, a PLL gives an accurate (not average) output frequency that is not necessarily an integer multiple of the reference. The required reference frequency must be fairly high, with a low factor, because the lock precision depends on frequent updates (or the output frequencfy may 'jump'). The PLL used for MSP430-USB builds 48MHz from a reference that is at least 1.5MHz (4MHz when using a crystal).

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