Hi All,
I was trying to achieve the following on MSP430f5255.
What I am getting on the logic analyzer is the following:
My code is as follows:
assert(timeout > 0); //Store current transmit interrupt enable uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; //Disable transmit interrupt enable HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); //Send start condition. HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; while(UCB2CTL1 & UCTXSTT); //wait for UCTXSTT to clear //HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; //while ((! (HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG ) ) ) ; HWREG8(baseAddress + OFS_UCBxTXBUF) = registerAddress; while ((! (HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG ) ) ) ; // hoping that the txbuff would be ready for the next instruction here. //__delay_cycles(30); //HWREG8(baseAddress + OFS_UCBxIFG) &= ~( UCTXIFG); //UCB2CTL1 |= UCTXSTP; // I2C stop condition // while (UCB2CTL1 & UCTXSTP); // Ensure stop condition got sent //while((! (HWREG8(baseAddress + OFS_UCBxIFG) & UCTXSTP ) )); //while(UCB2CTL1 & UCTXSTT); //wait for UCTXSTT to clear if( UCB2CTL1 & UCNACKIFG ) // check for NACKIFG. { UCB2CTL1 |= UCTXSTP; return; } //Poll for transmit interrupt flag. //while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; HWREG8(baseAddress + OFS_UCBxTXBUF) = value; while (!((HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG))) ; //while((! (HWREG8(baseAddress + OFS_UCBxIFG) & UCTXSTP ) )); //Check if transfer timed out if (timeout == 0) { UCB2CTL1 |= UCTXSTP;// release the bus return STATUS_FAIL; } //while (!(UCB2IFG & UCTXIFG)); //wait for UCTXIFG to set. UCB2CTL1 |= UCTXSTP; // I2C stop condition while (UCB2CTL1 & UCTXSTP); // Ensure stop condition got sent //Send single byte data. //HWREG8(baseAddress + OFS_UCBxTXBUF) = txData;
1.My suspicion is that the MSP is not ready to transmit the next byte. I am checking this by polling the TxIFG flagIs there any other way to do this so it works. ?
2. I was reading a section in the user guide and need some help understanding what it really implies.
Is this the solution to my problem ? Or is this just talking about two different transactions ? The slave device does not require repeated starts to be sent out.
Thanks,
Chinmay