I did use the Search function but did not find a suitable answer. I apologize in advance if I didn't search deep enough.
I am debugging a modified example project, msp430fr59xx_ta0_capture. It is running and I am getting the capture numbers. What I can't figure out is why are the numbers off? When VLO is used as ACLK source, I am getting 97-98 counts per capture with a 1 MHz SMCLK. Sounds about right; VLO is not exacly 10 kHz so who knows what should VLO/SMCLK really be? To verify the capture timing I configured ACLK to use LFXT, and the SMCLK to 8 MHz for better resolution, like so:
P3DIR |= BIT4;
P3SEL1 |= BIT4; // Output SMCLK so I can scope it
PJSEL0 = BIT4 | BIT5; // For XT1
// Clock System Setup for LFXT
CSCTL0_H = CSKEY >> 8; // Unlock CS registers
CSCTL1 = DCOFSEL_6; // Set DCO to 8 MHz
CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers
CSCTL4 &= ~LFXTOFF;
CSCTL0_H = 0x00; // Lock CS module (use byte mode to upper byte)
The project runs just fine but the captured numbers are 213-214 counts apart. They should be 8000000 / 32768 = 244 counts apart. The difference is like 13%! I started thinking, cycle count for ISR etc but that shouldn't matter, the timer counting is done in hardware, is continuous and independent of the CPU, and should go on in the background, and TA0CCR2 should update at rate 32768Hz counting at 8MHz.
Both clocks were verified using a scope, and they are indeed 32.768kGz and 7.998MHz. What is happening?
Thanks!
-P