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SPI B1 clock issues

eltury
Genius 3330 points
Other Parts Discussed in Thread: MSP430F2618, ADS7953

Greetings,

I'm using an MSP430F2618 at 8 Mhz. SPI clock at 4 Mhz. This is communicating over an extended SPI bus (TI app note  from 4Q 2011 "Extending the SPI bus for long-distance communication").

My bus driver is an ADN4665. I'm talking to an ADC (ADS7953) on the PCB with the MSP430 and on slave boards at the end of the cable run. Termination R is 200 ohms. I can have a maximum of 3 slave boards on the bus. This has been working but it's iffy. My "master" board works fine until I connect a slave. The slave works fine, but then the master gets weird and only recovers when I connect my scope probe to the SPI clock at the output of the micro. Some capacitance/clock skewing issue but I can't detect what is going on as yet.

So something about driving the bus terminated in a 200 ohm R cause a shift that makes things go haywire, but not on the unit at the end of the bus.

I really want to find the underlying issue and not have to tack a cap on my board to make delivery.

Any thoughts or suggestions would be appreciated.

  • 0
    Genius 3330 points
    Edit:
    The driver SPI is UCA1CLK. The receiver is UCB1CLK.
  • 0 in reply to eltury
    Guru 227245 points
    What do you mean with 'the master gets weird'? SPI has no handshake. The master sends a clock signal and its output and at the same time receives incoming data (whether there is someone sending or not).
    The received data might not be what is expected, but no way for any lock-up or such.

    How do you synchronize master and slave? I mean, what are the connections, besides the clock (master out to slave in) the master out to slave-in data (MOSI) and the master in from slave out data (MISO)? You need individual chip select signals (general digital I/O ports) controlled by software on the master and checked by software on the slave(s).
    Also, your line driver needs to propagate the chip select signal from master to slave and also be enabled by the chip select, and the receiver side needs to be individually muted by the same chip select it forwards to the slaves.

    So from the master, CLK and MOSI CSx go to the line driver and are forwarded to the slave, while CS also enables/disables the line receiver from this slave (MISO)
    I doubt the ADN4665 is the best choice, as you need three drivers and one receiver (with individual enable) per slave on the master side and three receivers and a driver on each slave side.
    For the ADuM we use for electric isolation of SPI signals, AD has multiple devices with different combinations of drivers and receivers in their portfolio. You might find something similar for the differential line.

    The ADN4665 is a current-mode transceiver. That means the termination resistor is mandatory. Without it, no current flows and signal voltage will latch-up. Other drivers use voltage mode (differential voltage is applied to the bus) where the termination is only needed on longer signal lines to avoid reflections. Current mode has other advantages such as constant load rather than current peaks at the signal edges. And it is immune to signal reflections. But having multiple receivers on a line is tricky.

    You may post your schematics (or at least the wiring concept) for further analysis.

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