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Timing of CPU and CPUX architecture

Peter Bägel
Prodigy 50 points

Hi all,

I'm inteessted in the internal timing of the CPU and CPUX architecture. I know the different cycle times for the different instructions, they are well documented. I like to look a bit deeper: What is on the internal busses (MAB, MDB) at the different phases of the clock cycles? Also: When will the read/write or other control lines change their states? I didn't find it up to now in any documentation.


Thanks, Peter

  • 0
    Guru 33653 points

    Peter Bägel said:

    I know the different cycle times for the different instructions, they are well documented.

    Are they well documented for CPUX?

        rra.b @R5         ; 3        rra.b @R5         ; 3
    nop               ; 1        rra.b @R5         ; 3
    rra.b @R5         ; 3        rra.b @R5         ; 3
    nop               ; 1        rra.b @R5         ; 3
    rra.b @R5         ; 3        rra.b @R5         ; 3
    nop               ; 1        rra.b @R5         ; 3
    rra.b @R5         ; 3        nop               ; 1
    nop               ; 1        nop               ; 1 
    rra.b @R5         ; 3        nop               ; 1
    nop               ; 1        nop               ; 1
    rra.b @R5         ; 3        nop               ; 1
    nop               ; 1        nop               ; 1
-------------------------    -------------------------
Total number of cycles 24    Total number of cycles 27

    Some info regarding MAB / MDB / Clock relation can be found in slau320 Programming Via the JTAG Interface

  • 0 in reply to zrno soli
    Guru 227245 points
    This makes no sense. I could perhaps construct an explanation for a clock cycle difference of 5 (even though there should be none at all), but not of 3.
  • 0 in reply to Jens-Michael Gross
    Guru 33653 points

    I lost significant time period for figuring out why bit-banging (that is working just fine on CPU) on CPUX is not working. Than I made CPUX cycle counter and everything (not covered by datasheet) become clear. I was also confused with CPUX constants.

    4443                         mova #0, R4             ; 2
    5443                         mova #1, R4             ; 2
    6443                         mova #2, R4             ; 1
    6442                         mova #4, R4             ; 1
                 
    A4000000                     adda #0, R4             ; 2
    A4000100                     adda #1, R4             ; 2
    E403                         adda #2, R4             ; 1
    A4000400                     adda #4, R4             ; 2

    D403                         cmpa #0, R4             ; 1
    94000100                     cmpa #1, R4             ; 2
    94000200                     cmpa #2, R4             ; 2
    94000400                     cmpa #4, R4             ; 2

  • 0 in reply to zrno soli
    Guru 227245 points
    Of course it is strange that the assembler sometimes uses the constant generator and sometimes not.
    I know that the constant generator is not working for some instructions and some values on 1x family (like push #8 won't work with the CG).
    It's possible that for some instructions, the addressing mode used for the constant generator access is not available. Most 'A' instructions, unlike their X.A extended versions, only work with (real) immediate values and registers. If the opcode contains no field for other addressing modes, the CG can't be used. This could explain the adda/cmpa anomaly. At least partially. And mova, to support all addressing modes, is actually multiple instructions. Which may explain the difference for 0/1 and 2/4.

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