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ADC12 noisy when in low power mode 3 vs. 1/0/active, why?

Other Parts Discussed in Thread: MSP430F5438A

Hi everyone,

I have an MSP430F5438A capturing a test tone of 1kHz using the ADC12 module. The ADC12 module is clocked from SMCLK/2. The trigger from the sample timer is sourced from Timer B. Timer B is sourced from ACLK. SMCLK is from the DCO/FLL referenced to XTAL1/ACLK.

If I use low power mode is 1, the stored samples are noise free - almost perfect 1kHz tone. If I then use low power mode is 3, to save more power, the stored samples are noisy. If I periodically enter lpm1, I see the noise go away.

My understanding is that the difference between lpm1 and lpm3 is that the DCO Generator is also off and that SMCLK is disabled. But why does it work at all? There is no frequency drift, just noise. To further prove this, if I increase the sample time the noise goes away. So it definitely appears to be an interaction between the SMCLK and the Sample&Hold. 

Additionally, I am thinking of testing lpm1+SMCLK vs lpm3+ADC12OSC, to see which is lowest power - if indeed lpm3+SMCLK is not a valid configuration. 

Your thoughts would be greatly appreciated. 

  • Hi James,

    Timer B decides when ADC samples will occur but the sample&hold times are based off of the ADC12CLK, which is sourced by SMCLK. If the sample time is too short than errata UCS7 may occur where a short ISR results in DCO drift and this could create the noise you are seeing. To alleviate this issue then try inserting a delay of at least 3 x reference clock periods before exiting from the ADC ISR. Or simply keep a high sample time since that is already shown to fix the issue, you will definitely be getting the lowest power by utilizing LPM3.

    Regards,
    Ryan
  • Hi Ryan,

    Thank you for your reply. I am glad you agree that some sort of SMCLK drift seems to be introducing noise in my ADC measurements.

    To clarify, as the guidance documents are somewhat confusing in this respect, lpm3 + adc using smclk is supported? And it will just request the clock when required? 

    I also wonder if its UCS7 - could it just be the startup time of the DC generator? Because what I see in my tests that if I change the sample period from 16 adc clocks to 128 adc clocks the noise goes away. But this is significantly less than 3x ref clock periods (32us vs. 92us). 

    As for your advice, I am using a DMA channel to fetch ADC samples to RAM. So I think my only parameter to vary is the sample timer duration to account for any drift/startup time allowance needed for smclk, which is currently 16 x ADC12CLK, to a level where the noise is sufficient for my application. 

    I'd appreciate your further response to resolve my issue.

    Many thanks,James

  • Hi James

    James Hillman said:
    lpm3 + adc using smclk is supported? And it will just request the clock when required? 

    I apologize, I don't think I answered this in my initial post correctly.  The ADC12SHSx bit determines whether a sample is started through the ADC12SC bit or a timer source.  At this point the ADC12 will take samples for a given amount of ADC12CLK cycles based on the ADC12SHT0x bits.  However, the device is still in LPM during this time and will only wake up and service the interrupt flag after the conversion has been completed.  Therefore LPM3 is not recommended with an ADC12CLK sourced from SMCLK since said clock is disabled in this low power state as stated by Table 1-2 of the Family User's Guide.

    James Hillman said:
    I am using a DMA channel to fetch ADC samples to RAM

    What you could do instead is use timer B to exit LPM3, begin a conversion and enter LPM0/1, exit LPM0/1 when the conversion is finished and the ADC samples have been stored in RAM, and then re-enter LPM3.  This will produce the least noise and power consumption possible.

    James Hillman said:
    But this is significantly less than 3x ref clock periods (32us vs. 92us). 

    This could be a "best case" recommendation, where faster times could still possibly work as well.

    Regards,

    Ryan

  • Hi Ryan,

    I am still not satisfied with this answer.

    Ryan Brown1 said:
     Therefore LPM3 is not recommended with an ADC12CLK sourced from SMCLK since said clock is disabled in this low power state as stated by Table 1-2 of the Family User's Guide.

    I agree from your table. But if you look at table 5-1, it suggests that in lpm3 SMCLK can be requested. 

    Another way to think about this is, if the clock is disabled, then how am I getting conversions at all? I appreciate sometimes the samples are noisy. The noise reduces by increasing the sample time period (e.g. 16x ADC12CLK to 128x ADC12CLK). 

    So my architecture is Timer B (aclk) ->ADC Trigger->ADC (smclk)->DMA Trigger->DMA Channel-> RAM = no Interrupts. If your comment was true, then I would never ever get data as I never exit lpm3. It certainly seems that in lpm3 the ADC12 module can still request the SMCLK to be turned back on. Please can you confirm this or otherwise explain what I am seeing? 

    My solution for now is to use a higher sample time period to reduce the noise in the signal, but this is consumes more power. My concern from what you are saying is that I must understand if this is some sort of fluke/undefined/undetermined use of the MSP430. If you could please double check this/find a strong evidence for this, then we can agree the source of the adc noise which I suggest currently is due to the wakeup time of the DCO (~3.5us). 

    Best Regards, James 

  • Hello James,

    Table 5-1 does look promising and seems to imply that SMCLK may be on while in LPM3, which then explains the noise due to the DCO wakeup time.  SMCLKREQEN is zero by default, are you intentionally setting this pin in your code?  If this is the case then you are most likely not benefiting from any power savings by being in LPM3 as compared to LPM0/1.

    If what you are saying is true and you really are in true LPM3 mode without any interrupts then the DCO should never wake up. It may be possible that SMCLK never turns off properly due to errata UCS6, are you by any chance using a USCI configured in UART mode in your project?

    Can you use ACLK to source ADC12CLK or would 32768 Hz be too slow for your application?

    Regards,
    Ryan

  • Did you calculate the minimum necessary sample time? If not then do.

    What I could imagine is if something has to be started up it can be possible that a (short) piece of the sampling time is missing, when you are already on the edge you can get this behavior.
  • Hi Ryan - many thanks for your continued support. 

    Ryan Brown1 said:

    Table 5-1 does look promising and seems to imply that SMCLK may be on while in LPM3, which then explains the noise due to the DCO wakeup time.  SMCLKREQEN is zero by default, are you intentionally setting this pin in your code?  If this is the case then you are most likely not benefiting from any power savings by being in LPM3 as compared to LPM0/1.

    I am seeing a power saving between LPM1 and LPM3 - and this is why I really want to get to the bottom of this. According to Table 5-11 SMCLKREQEN is one by default. 

    Ryan Brown1 said:

    If what you are saying is true and you really are in true LPM3 mode without any interrupts then the DCO should never wake up. It may be possible that SMCLK never turns off properly due to errata UCS6, are you by any chance using a USCI configured in UART mode in your project?

    Ryan - thanks for this thought. I am seeing a power difference LPM0, LPM1 and LPM3. If SMCLK is staying on, then what else is turning off to reduce my power in LPM3? I do however have a UART mode USCI and I will investigate this further - right now, and respond soon.  

    Ryan Brown1 said:

    Can you use ACLK to source ADC12CLK or would 32768 Hz be too slow for your application?

    ACLK is too slow for my application. 

    Leo Bosch said:

    Did you calculate the minimum necessary sample time? 

    I did. But completely agree with your scenario. And I am reasonably happy to increase the sample time to mitigate the noise I see, if indeed LPM3 + ADC SMCLK is a supported use of the MSP430.

    What is interesting is that I feed the output of my op-amp directly to the adc input. So I am not sure what Rs truly is. To confuse matters further, I have tried a different op-amp part and design, with a 82Ohm series resistor with the adc input and I did not see this issue i.e. no noisy measurements with smclk adc + lpm3. One might just confused that the other op-amp has a resistance higher than 82Ohms, but then, it doesn't explain why changing the lpm from 3 to 1 fixes the noise issue. So I believe this to be a secondary effect. What do you think Leo?

  • When the time between exit LPM and the start of conversion matters, then in my opinion it must have to do with the analogue (and his channel switch) and/or port startup.
    I don’t know exactly what is powered down when LPM3, but that will be in the User’s Manual, didn’t check this for now and I think you have invested already a lot of time in it so will know. The ADC goes down if not needed but I think that doesn’t differ from LPM level.
    Sourcing from an Op-Amp via this low resistance will need a very short sampling time, so this can’t be the reason.
    It’s also possible that the DCO is -for a short time- too fast, which shorts the sampling time.

    Another possibility I was thinking about, but it depend on your power source and is maybe not applicable here, but when lowering/rising the power need some (bad) power supplies/sources can give a hick or oscillates for a short time.
    And the same can apply to the DVcc pin of the MCU, power-up results in heavily (short) power need, when not properly decoupled you can get some noise on your AVcc.

    And maybe from everything a little bit.
  • Leo Bosch said:
    Sourcing from an Op-Amp via this low resistance will need a very short sampling time, so this can’t be the reason.
    It’s also possible that the DCO is -for a short time- too fast, which shorts the sampling time.

    Hi Leo. I completely agree with your comments. Thank you for thinking about my problem.

    Leo Bosch said:
    Another possibility I was thinking about

    Good thinking. But interesting in my scenario, I get my best samples during the noisy flash writing/power spike on the regulators. Its the reverse. And in fact, the first time I saw this is it was spikes due to this loading your describing. When I saw it again, with a different front end again, I immediately thought of this again, but as I say its different. 

    Ryan Brown1 said:
    UCS6 uart idle mode

    Hi Ryan, I have tested this and found no change in my adc noise. I have also tested using the internal voltage reference for the ADC and this made no difference. I would be greatful if you could at least confirm that using lpm3 + adc smclk is valid i.e. intend to be used like this. Then I can sleep easy knowing its just about getting my sample time correct for the worst case front end and dco wake up.

    Thanks all, James

  • James Hillman said:
    According to Table 5-11 SMCLKREQEN is one by default. 

    I apologize James, I shouldn't have assumed the initial state of the SMCLKREQEN bit.

    James Hillman said:
    what else is turning off to reduce my power in LPM3?

    Knowing now that SMCLK is active and sourced from the DCO, I agree with you that the DCO wakeup time has a part in this issue.

    Ryan.

  • James Hillman said:
    I would be greatful if you could at least confirm that using lpm3 + adc smclk is valid i.e. intend to be used like this.

    Since the SMCLKREQEN bit is set to activate SMCLK while operating in LPM3 it is safe to assume that using the ADC12 sourced by the SMCLK while in LPM3 is a valid format.

    Ryan

  • James, you already investigated a lot.
    “It’s the reverse.” is impossible. I don’t want to be impolite but did you measured this well, proper probe grounding? Would be interesting to see your hardware and especially ground routing.

    You have noise, the sample time is short 1-2uS, would be interesting to see the noise short before and during the sample time. If possible output Timer B to a port pin and trigger an oscilloscope with it to see the signals at exactly this time.

    What happens when you measure a shorted ADC channel, the internal voltage or the temperature sensor (voltage over sensor is less influenced by spikes)?
  • Leo Bosch said:
    “It’s the reverse.” is impossible. I don’t want to be impolite but did you measured this well, proper probe grounding? Would be interesting to see your hardware and especially ground routing.

    Hi Leo. No offence taken. I only look at the signal in the data sampled rather than a scope - I wasn't able to see this noise on a scope. I think I didn't explain very well - I just mean I get noise in the samples when I am not writing to flash/exiting lpm in software. When I write data from RAM to the external flash chip the MSP430 exits lpm3 and is either in active mode or lpm1. In these modes the smclk remains active and therefore my samples do not suffer the noise. Similarly, if Timer B uses SMCLK rather than ACLK, I know longer get noisy samples, because SMCLK remains on all the time. 

    Leo Bosch said:
    What happens when you measure a shorted ADC channel, the internal voltage or the temperature sensor (voltage over sensor is less influenced by spikes)?

    If I measured a shorted channel (either through the front end or on the adc directly) or a signal directly into the adc (or the internal avcc/2) I see no noise at all. A constant value in the case for AVCC/2 and signal directly. 

    I actual have this front end design for two different layouts. Annoyingly, I don't see this issue on the other layout. The MSP430 revisions are different. The one with this issue is H and the one without is E. I think, some MSPs are going to be better than others, and some layouts better than others in terms of noise during DCO wakeup - so maybe I shouldn't investigate to much further. What do you think Leo and Ryan?

  • James Hillman said:
    If I measured a shorted channel (either through the front end or on the adc directly) or a signal directly into the adc (or the internal avcc/2) I see no noise at all. A constant value in the case for AVCC/2 and signal directly. 

    In this case the noise is not coming from inside the MSP but from outside and also not due to an improper ADC sample and conversion. The short on ‘front end’ here could be an exception, to clarify this I need more information about the analogue schematic.

    The layout difference increases the ‘outside’ suspect.

    And the ‘outside’ source will be power-up spikes/oscillation.

    The reason could be many; Wrong placed cap’s, too much or too less cap’s, wrong cap value or type, inductors or trace inductance, mixed digital and analogue routing/planes, etc.

    When using linear voltage regulators, and especially when you use in the two layouts different types/routing, have a look at the decoupling capacitors on both side (in & out), value, type and routing.

  • James Hillman said:
    I actual have this front end design for two different layouts. Annoyingly, I don't see this issue on the other layout. The MSP430 revisions are different. The one with this issue is H and the one without is E.

    What this could mean is that your issue indeed involves an errata whose state has changed from revision E to H.  The odd thing is that your condition is worse in the later revision suggesting that a fixed errata in specific now causes your issue or that you are using an errata to your advantage with the previous revision.  Anyways, like Leo has mentioned, it is very hard to tell without knowing all of the exact differences between the two layouts.

    Regards,

    Ryan

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