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BSL SLAA450 EXAMPLE MSP430G2XXX

Other Parts Discussed in Thread: MSP430F2274

Good day,

I'm asking if someone has trying succesfuLly the example in the SLAA450C with the MSP430G2XXX at the end of the text, I have two issues.

1. When I send the SYNC character from host to device 0xBA, actually reads 0x72h, IT looks like the lost of two bits.
2. I don't know how to use the hex2bin, I can find de hex file.

As you can see I'm a newvie in BSL matters, and I would like to check the viability of the example, I'm working with IAR 5.4


REGARDS.

ANDRÉS FELIPE RODRÍGUEZ

  • Running vBSL.docx

    Hi Andres,

    I just tested the vBSL in SLAA450 and made this document explaining step-by-step how to do it. 

    If you are receiving incorrect data from the PC, make sure that your DCO is calibrated properly (and make sure that your host is sending the right data at the right baudrate using a logic analyzer or oscilloscope). 

    This example is from the G2xx1 code examples and it can re-calibrate the device (if you have a crystal). 

    msp430g2xx1_dco_flashcal.c
    /* --COPYRIGHT--,BSD_EX
     * Copyright (c) 2012, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     *******************************************************************************
     * 
     *                       MSP430 CODE EXAMPLE DISCLAIMER
     *
     * MSP430 code examples are self-contained low-level programs that typically
     * demonstrate a single peripheral function or device feature in a highly
     * concise manner. For this the code may rely on the device's power-on default
     * register values and settings such as the clock configuration and care must
     * be taken when combining code from several examples to avoid potential side
     * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
     * for an API functional library-approach to peripheral configuration.
     *
     * --/COPYRIGHT--*/
    //******************************************************************************
    //  MSP430G2xx1 Demo - DCO Calibration Constants Programmer
    //
    //  NOTE: THIS CODE REPLACES THE TI FACTORY-PROGRAMMED DCO CALIBRATION
    //  CONSTANTS LOCATED IN INFOA WITH NEW VALUES. USE ONLY IF THE ORIGINAL
    //  CONSTANTS ACCIDENTALLY GOT CORRUPTED OR ERASED.
    //
    //  Description: This code re-programs the G2xx1 DCO calibration constants.
    //  A software FLL mechanism is used to set the DCO based on an external
    //  32kHz reference clock. After each calibration, the values from the
    //  clock system are read out and stored in a temporary variable. The final
    //  frequency the DCO is set to is 1MHz, and this frequency is also used
    //  during Flash programming of the constants. The program end is indicated
    //  by the blinking LED.
    //  ACLK = LFXT1/8 = 32768/8, MCLK = SMCLK = target DCO
    //  //* External watch crystal installed on XIN XOUT is required for ACLK *//
    //
    //           MSP430G2xx1
    //         ---------------
    //     /|\|            XIN|-
    //      | |               | 32kHz
    //      --|RST        XOUT|-
    //        |               |
    //        |           P1.0|--> LED
    //        |           P1.4|--> SMLCK = target DCO
    //
    //  A. Dannenberg
    //  Texas Instruments Inc.
    //  May 2010
    //  Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 3.42A
    //******************************************************************************
    #include <msp430.h>
    
    #define DELTA_1MHZ    244                   // 244 x 4096Hz = 999.4Hz
    #define DELTA_8MHZ    1953                  // 1953 x 4096Hz = 7.99MHz
    #define DELTA_12MHZ   2930                  // 2930 x 4096Hz = 12.00MHz
    #define DELTA_16MHZ   3906                  // 3906 x 4096Hz = 15.99MHz
    
    unsigned char CAL_DATA[8];                  // Temp. storage for constants
    volatile unsigned int i;
    int j;
    char *Flash_ptrA;                           // Segment A pointer
    void Set_DCO(unsigned int Delta);
    
    int main(void)
    {
      WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
      for (i = 0; i < 0xfffe; i++);             // Delay for XTAL stabilization
      P1OUT = 0x00;                             // Clear P1 output latches
      P1SEL = 0x10;                             // P1.4 SMCLK output
      P1DIR = 0x11;                             // P1.0,4 output
    
      j = 0;                                    // Reset pointer
    
      Set_DCO(DELTA_16MHZ);                     // Set DCO and obtain constants
      CAL_DATA[j++] = DCOCTL;
      CAL_DATA[j++] = BCSCTL1;
    
      Set_DCO(DELTA_12MHZ);                     // Set DCO and obtain constants
      CAL_DATA[j++] = DCOCTL;
      CAL_DATA[j++] = BCSCTL1;
    
      Set_DCO(DELTA_8MHZ);                      // Set DCO and obtain constants
      CAL_DATA[j++] = DCOCTL;
      CAL_DATA[j++] = BCSCTL1;
    
      Set_DCO(DELTA_1MHZ);                      // Set DCO and obtain constants
      CAL_DATA[j++] = DCOCTL;
      CAL_DATA[j++] = BCSCTL1;
    
      Flash_ptrA = (char *)0x10C0;              // Point to beginning of seg A
      FCTL2 = FWKEY + FSSEL0 + FN1;             // MCLK/3 for Flash Timing Generator
      FCTL1 = FWKEY + ERASE;                    // Set Erase bit
      FCTL3 = FWKEY + LOCKA;                    // Clear LOCK & LOCKA bits
      *Flash_ptrA = 0x00;                       // Dummy write to erase Flash seg A
      FCTL1 = FWKEY + WRT;                      // Set WRT bit for write operation
      Flash_ptrA = (char *)0x10F8;              // Point to beginning of cal consts
      for (j = 0; j < 8; j++)
        *Flash_ptrA++ = CAL_DATA[j];            // re-flash DCO calibration data
      FCTL1 = FWKEY;                            // Clear WRT bit
      FCTL3 = FWKEY + LOCKA + LOCK;             // Set LOCK & LOCKA bit
    
      while (1)
      {
        P1OUT ^= 0x01;                          // Toggle LED
        for (i = 0; i < 0x4000; i++);           // SW Delay
      }
    }
    
    void Set_DCO(unsigned int Delta)            // Set DCO to selected frequency
    {
      unsigned int Compare, Oldcapture = 0;
    
      BCSCTL1 |= DIVA_3;                        // ACLK = LFXT1CLK/8
      TACCTL0 = CM_1 + CCIS_1 + CAP;            // CAP, ACLK
      TACTL = TASSEL_2 + MC_2 + TACLR;          // SMCLK, cont-mode, clear
    
      while (1)
      {
        while (!(CCIFG & TACCTL0));             // Wait until capture occured
        TACCTL0 &= ~CCIFG;                      // Capture occured, clear flag
        Compare = TACCR0;                       // Get current captured SMCLK
        Compare = Compare - Oldcapture;         // SMCLK difference
        Oldcapture = TACCR0;                    // Save current captured SMCLK
    
        if (Delta == Compare)
          break;                                // If equal, leave "while(1)"
        else if (Delta < Compare)
        {
          DCOCTL--;                             // DCO is too fast, slow it down
          if (DCOCTL == 0xFF)                   // Did DCO roll under?
            if (BCSCTL1 & 0x0f)
              BCSCTL1--;                        // Select lower RSEL
        }
        else
        {
          DCOCTL++;                             // DCO is too slow, speed it up
          if (DCOCTL == 0x00)                   // Did DCO roll over?
            if ((BCSCTL1 & 0x0f) != 0x0f)
              BCSCTL1++;                        // Sel higher RSEL
        }
      }
      TACCTL0 = 0;                              // Stop TACCR0
      TACTL = 0;                                // Stop Timer_A
      BCSCTL1 &= ~DIVA_3;                       // ACLK = LFXT1CLK
    }
    

    Regards,

    Luis R

  • Hi Luis,

    Thanks for your help, I'm going to try and I will tell you, how the things are going.

    Thanks.

    Andrés Felipe

  • Hi Luis,
    I follow your indications and works perfect, thanks, now I want to try with the msp430f2274, but I wonder how the program knows when to finish the rx to evaluate the rCHKSUM, must be with a counter but I can not see it, I don't know assebler lenguage.

    Thanks

    ANDRÉS FELIPE
  • Hi Andres,

    This is explained in SLAA450:

    2.2.1.4 Receiving and Writing New User Data After the erase happens, the BSL is ready to accept user data, one byte at a time. There is no handshake in place, so the system expects exactly the right amount of data, which is total available main flash size minus 2 bytes, starting at lowest flash address all the way up to, but excluding, the reset vector.

     

    The comments in the code are also useful to understand the functionality:

    CFW_Range   cmp     #0FFFEh, rPoint         ; Pointer to Reset Vector?
                jeq     CFW_Done                ; Skip and exit Write
                mov.b   rxData,0(rPoint)        ; Write 8 bit data to flash
    
    CFW_COMM
    CFW_Xor     xor.b   @rPoint+,rCHKSUM        ; xor checksum and inc pointer
                ;inc    rPoint                  ; inc done above w/ Auto increment
                jmp     CFW_w4d                 ; wait for next byte
    
    CFW_Done    ; ================================================================
                ; rx'ed byte for adress 0xffe (RESET) contains checksum
                ; ================================================================
                cmp.b   rxData, rCHKSUM         ; XOR'ing calc checksum with sent
                jeq     LoadACK                 ;  should result in ZERO if match


    As you can see, the keeps track of the current address in "rPoint" and when it gets to FFFE, it receives the Checksum.

    Regards,

    Luis R

     

  • Hi Luis,

    I've been trying to change the BSL, for receive data form a SPI memory (at25f1024), but alwasy jump to the main, when I look the desassembly program, it works just to the addres 0x10C0, I guess that is because the SPI comunication uses a lot of call function.

    I'm using the msp430f2274.

    I will send you the program, please any advice wold be very helpfull.

    Thanks

    ;*******************************************************************************
    ;   G2xxx BSL is a Boot Strap Loader for MSP430G2xxx based on software UART with
    ;      small Flash Footprint so that it fits into info memory (256 - 2 Byte)
    ;
    ;                MSP430G2xxx
    ;             -----------------
    ;         /|\|                 |
    ;          | |        P1.0/P1.6|---> LED (only used in MAIN not in BSL)
    ;          --|RST              |
    ;            |                 |
    ;            |      BSLPIN/P1.3|<--- Enable Pin / S2 on LaunchPad
    ;            |                 |
    ;            |                 |
    ;            |          rX/P1.1|<--- UART 9600 8N1
    ;            |          tX/P1.2|---> rx/tx swapped on LaunchPad!
    ;             -----------------
    ;
    ;
    ;   Texas Instruments
    ;   Built with IAR 5.20.1
    ;*******************************************************************************
    #include <msp430.h>  ; Include device header file
    ;-------------------------------------------------------------------------------
    ;-------------------------------------------------------------------------------
                RSEG    CSTACK                  ; Define stack segment
    ;-------------------------------------------------------------------------------
    ;-------------------------------------------------------------------------------
                ;Main / Customer Application
    ;-------------------------------------------------------------------------------
    LED         EQU     BIT0                    ; RED LED
    ;LED        EQU     BIT6                    ; GREEN LED
    ;-------------------------------------------------------------------------------
                RSEG    CODE                    ; User Application
                ; ================================================================
                ; Never place any code / data between RSEG CODE (.text) and main
                ; label. This adress is used as start adress for user code
                ; ================================================================
    ;-------------------------------------------------------------------------------
                ; Customer Application starts here
    main        nop                             ; User Code needs to start here!
       bis.b   #LED,&P1DIR             ; Make pin an output
                mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop Watchdog Timer
    Mainloop    xor.b   #LED,&P1OUT             ; Toggle LED
                mov.w   #0FFFFh,R15             ; Delay to R15
    DelayL1     dec.w   R15                     ; Decrement R15
                ; ================================================================
                ; Note that any Register and RAM can be used
                ; ================================================================
                inc.w   R15                     ; Increment R15
                dec.w   R15                     ; Decrement R15
                jnz     DelayL1                 ; Delay over?
                jmp     Mainloop                ; Again
    ;-------------------------------------------------------------------------------
                ;END of Main / Customer Application
    ;-------------------------------------------------------------------------------
    ;-------------------------------------------------------------------------------
                RSEG      BSL         ;BSL Application
    ;-------------------------------------------------------------------------------
    ;           Flash Main Segment Start Adress (see datasheet)
    FLASHSTART  EQU      main                   ; Lowest main flash address
    ;           CPU registers used for BSL
    #define     RXTXData  R4
    //#define     BitCnt    R5
    #define     rxData    R6
    //#define     rCHKSUM   R7
    #define     rPoint    R8
    #define     rTemp     R7
    #define     Addr      R5
    //////;           Conditions for 9600 Baud HW/SW UART, MCLK 1 MHz
    //////;           1 MHz / 9600 = 104.15 Cycles per bit
    //////BITTIME_5   EQU     52                      ; 0.5 bit length
    //////BITTIME     EQU     104                     ; 104 us
    //////NACKCYCL    EQU     BITTIME*2               ; 2 bits low: start + 1 data bits
    //////                                            ;  0 + (1111 1110)b = 0xFE
    //////ACKCYCL     EQU     BITTIME*4               ; 4 bits low: start + 3 data bits
    //////                                            ;  0 + (1111 1000)b = 0xF8
    //////                                            ; Meas: Puls 2us too long but no
    //////                                            ;  impact at 104us Bittime
    //////RXD         EQU     02h                     ; RXD on P1.1
    //////TXD         EQU     04h                     ; TXD on P1.2
    BSLPIN      EQU     BIT3                    ; BSL entry on P1.3 LOW (Use pullup)
    nCS         EQU     BIT6
    //////;           Command number definition
    //////CMD_SYNC    EQU     0BAh
    ////;-------------------------------------------------------------------------------
    ////;           Jump table for UART Bit detection
    ////;-------------------------------------------------------------------------------
    ////RX_Count    DB      RX_Edge-RX_Edge          ; Special for TA
    ////            DB      RX_Bit-RX_Edge           ; RX First Data Bit
    ////            DB      RX_Bit-RX_Edge           ;
    ////            DB      RX_Bit-RX_Edge           ;
    ////            DB      RX_Bit-RX_Edge           ;
    ////            DB      RX_Bit-RX_Edge           ;
    ////            DB      RX_Bit-RX_Edge           ;
    ////            DB      RX_Bit-RX_Edge           ;
    ////            DB      RX_Bit-RX_Edge           ;
    ////            DB      RX_Comp-RX_Edge          ; RX Complete, process RX data
    ;-------------------------------------------------------------------------------
    ;           Start of BSL Code
    ;-------------------------------------------------------------------------------
    BeginOfInfo jmp     $                       ; Safety: Avoid code run through
    RESET
                bit.b   #BSLPIN,&P1IN           ; Pin low invokes BSL
    BslEntry?   jz      InvokeBsl
                br      #main                   ; Exit BSL if pin not set
    ;-------------------------------------------------------------------------------
    ;           BSL Invoked
    ;-------------------------------------------------------------------------------
    InvokeBsl   mov.w   #600h,SP                ; Init Stackpointer to top of RAM
                                                ; RAM: 0x27f - 0x200
    //UnlockFlash mov.w   #FWKEY+00h,&FCTL3       ; LOCK=0, all others 0
    StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop Watchdog Timer
    SetupDCO    ; Set DCO to calibrated 1 MHz:
                clr.b   &DCOCTL                 ; Lowest DCOx and MODx settings
                ; ================================================================
                ; Note that the user needs to ensure that DCO Cal Data is not
                ;  erased during debugging - Read out from InfoA and hardcode
                ;  two bytes in move commands below.
    //            mov.b   #0A8h,&DCOCTL    ; Copy from address 0x010FEh
    //            mov.b   #086h,&BCSCTL1   ; Copy from address 0x010FFh
                ; Replace YOUR_DEVICE_VALUE with values gathered from actual
                ;  device. Values look like that: 0b3h and 086h
                ;  (Options -> FET Debugger -> Attach to runnning target)
                ; ================================================================
                ; ================================================================
                ; For Mass production please enable cal data readout directly from
                ;  InfoA. Empty devices should be programmed without erasing flash
                ;  before. If erased first, CAL data is lost. But can be restored
                ;  with FlashPro430 / GangPro430 programmers. www.elprotronic.com
                ;mov.b   &CALDCO_1MHZ,&DCOCTL   ; Set DCO step + modulation
                ;mov.b   &CALBC1_1MHZ,&BCSCTL1  ; Set range
                ; ================================================================
    ;OutputSMCLK bis.b   #BIT4,&P1DIR           ; Output SMCLK to check Frequency
    ;            bis.b   #BIT4,&P1SEL
    //SetupPins   bis.b   #RXD,&P1SEL             ; Rx pin special function
    //            bis.b   #TXD,&P1DIR
    //            bis.b   #TXD,&P1OUT
    //SetupTA0    ;CC Input0: Capture on falling Edge
    //            mov.w   #CM_2+CCIS_0+SCS+CAP,&TACCTL0
    //            ;Timer in Continuous mode, Clock Source is SMCLK
    //            bis.w   #TASSEL_2+MC_2+TACLR,&TACTL
    //InitRx      mov.w   #RX_Count,BitCnt        ; UART Bit Branch Pointer
    SPISetup        bis.b   #031h,&P3SEL            ; P3.0,4,5 USCI_A0 option select
                    bis.b   #041h,&P3OUT
                    bis.b   #040h,&P3DIR            ; P3.6 output direction   
                                    
                    bis.b   #UCCKPL+UCMSB+UCMST+UCSYNC,&UCA0CTL0 ; 3-pin, 8-bit SPI mast   
                    bis.b   #UCSSEL_2,&UCA0CTL1                  ; SMCLK
                    mov.b   #02h,&UCA0BR0
                    clr.b   &UCA0BR1                             ;
                    bic.b   #UCSWRST,&UCA0CTL1                   ; **Initialize USCI state machine**
    ;-------------------------------------------------------------------------------
    MainBsl             ; BSL Main Loop
    ;-------------------------------------------------------------------------------
    //Wait4sync   call    #RxOneByte
    //
    //SyncCmd?    cmp     #CMD_SYNC,rxData        ; Sync command received?
    //            jne     BSLEnd                  ; Exit BSL if no Sync Byte
    ;-------------------------------------------------------------------------------
    CmdFct_Erase        ; Erase main flash and restore interrupt vectors
    ;-------------------------------------------------------------------------------
                ; erase from bottom up
                mov.w   #FLASHSTART, rPoint     ; FLASH start address
    EraseSeg    //mov     &FWKEY+ERASE,&FCTL1     ; ERASE=1. Erase Segment
                ; Start praying here that nothing happens during next CPU cycles
                mov.b   #0h,0(rPoint)           ; Start erase with dummy write
                cmp.w   #0FE00h, rPoint         ; Interrupt vector segment just erased?
                jge     WrtRstVec               ; Restore it!
                add.w   #512,rPoint             ; Next segment (add segment size)
                jmp     EraseSeg                ; Repeat segment erase
    WrtRstVec   //mov     #FWKEY+WRT,&FCTL1       ; WRT=1. Write to segment
                mov     #RESET,&0FFFEh          ; Point reset vector to BSL
                ; You can stop praying here. Everything went fine once PC is here
                ; ================================================================
                ; Erasing Flash and rewriting vectors take approx 16 ms
                ;  Make sure to wait this time before new data is sent to MSP430
                ;  The UART function is placed in flash thus preventing access
                ;  to it while flash erase / write.
                ; ================================================================
    ;-------------------------------------------------------------------------------
    CmdFct_Write        ; Write 512 - 2 Byte to Main memory
    ;-------------------------------------------------------------------------------
                ;mov    #FWKEY+WRT,&FCTL1       ; Writing is still enabled
                ; Keeping WRT enabled w/o writing does not account into write time
                mov     #FLASHSTART,rPoint      ; Point to first position in FLASH
    //            clr     rCHKSUM                 ; Init Checksum
                ; ================================================================
                ; Ensure a minimum delay of 16 ms between SYNC and first byte
                ; ================================================================
    CFW_w4d     call    #RxOneByte
    CFW_Range   cmp     #0FFFEh, rPoint         ; Pointer to Reset Vector?
                jeq     CFW_Done                ; Skip and exit Write
    //            mov.b   rxData,0(rPoint)        ; Write 8 bit data to flash
                mov.b   &UCA0RXBUF,0(rPoint)
    //CFW_COMM
    //CFW_Xor     xor.b   @rPoint+,rCHKSUM        ; xor checksum and inc pointer
                ;inc    rPoint                  ; inc done above w/ Auto increment
                inc     Addr
                jmp     CFW_w4d                 ; wait for next byte
    CFW_Done    ; ================================================================
                ; rx'ed byte for adress 0xffe (RESET) contains checksum
                ; ================================================================
    //            cmp.b   rxData, rCHKSUM         ; XOR'ing calc checksum with sent
    //            jeq     LoadACK                 ;  should result in ZERO if match
    //
    //LoadNACK    mov.w   #(NACKCYCL/3),rTemp     ; Delay cycles to rTemp
    //            jmp     SendACK
    //LoadACK     mov.w   #(ACKCYCL/3),rTemp      ; /3 because 3 CPU cycles per loop
    //                                            ;  count required
    //
    //SendACK     bic.b   #TXD,&P1OUT             ; Let PC know about success
    //DelayACK    dec.w   rTemp                   ; Decrement rTemp
    //            jnz     DelayACK                ; Delay over?
    //            bis.b   #TXD,&P1OUT
                ; ================================================================
                ; Reset sequence required to exit BSL
                ; Do not jmp to main here - system is not in its initial state!
                ; ================================================================
    BSLEnd      ;jmp     MainBsl                ; Start BSL over again
                clr     WDTCTL                  ; Exit BSL by issuing RESET
                ; ================================================================
                ; Reset sequence required to exit BSL
                ; Do not jmp to main here - system is not in its initial state!
                ; ================================================================
    ;-------------------------------------------------------------------------------
    //RxOneByte   ; CCR0/UART ISR, RXTXData Buffer holds UART Data
    ;-------------------------------------------------------------------------------
    //Wait4CCIFG  bit.w   #CCIFG, &TACCTL0        ; Test CCIFG Bit
    //            jz      Wait4CCIFG
    //
    //            add.w   #BITTIME,&TACCR0        ; Bit time till next bit
    //            bic.w   #CCIFG, &TACCTL0        ; Clear IFG
    //
    //            mov.b   @BitCnt+,rTemp          ; Branch To Routine
    //            add     rTemp,PC                ; Branch To Routine
    //
    //RX_Edge     bic.w   #CAP+CCIFG,&TACCTL0     ; Switch to Compare mode
    //            add.w   #BITTIME_5,&TACCR0      ; First Databit 1.5 Bits from edge
    //            jmp     Wait4CCIFG              ;
    //
    //RX_Bit      bit.w   #SCCI,&TACCTL0          ; Get bit waiting in SCCI
    //            rrc.b   RXTXData                ; Store received bit
    //            jmp     Wait4CCIFG              ;
    //
    //RX_Comp     ; Byte received. Store and enable next rx cycle
    //            bis.w   #CAP,&TACCTL0           ; Switch to Capture mode
    //            mov.w   #RX_Count,BitCnt        ; RX_Count --> Branch Pointer
    //            mov.b   RXTXData,rxData         ; Copy from Bit to byte buffer
    //RxDone      ret                             ;
    spi_wr      bit.b   #UCA0TXIFG,&IFG2        ; USCI_A0 TX buffer ready?
                jz      spi_wr                  ; Jump --> spi_wrbuffer not ready            
                mov.b   RXTXData,&UCA0TXBUF
    Rx          bit.b   #UCA0RXIFG,&IFG2        ; USCI_A0 TX buffer ready?
                jz      Rx
                bic.b   #UCA0RXIFG,&IFG2        ; Confirmado, es RX
    RxDone      ret
    RxOneByte   bis.b   #nCS,&P3OUT            ; be aware that nCS = 1 
                bic.b   #nCS,&P3OUT            ; ssert low    nCS = 0
                mov.b   #003h,RXTXData              ;
                call    #spi_wr                ; send READ command 
                MOV.b   #0feh,RXTXData                                     
                call    #spi_wr                ; send READ command 
                mov     Addr,rTemp                ; calculate high byte and ...
                SWPB    rTemp
                mov.w   rTemp,RXTXData
                call    #spi_wr                ; send READ command 
                mov.b   Addr,RXTXData
                call    #spi_wr                ; send READ command             
                mov.b   #077h,RXTXData
                call    #spi_wr                ; send READ command 
                bic.b   #nCS,&P3OUT            ; ssert low    nCS = 0              comienza stop
                bis.b   #nCS,&P3OUT            ; be aware that nCS = 1             fin stop
    //            mov.b   &UCA0RXBUF,rxData           ; Mirar si es la dirección o es el valor de la variable
    rdDone      ret //jmp     CFW_Range
    ;-------------------------------------------------------------------------------
    ;           Interrupt Vectors
    ;-------------------------------------------------------------------------------
                COMMON  INTVEC                  ; Interrupt Vectors
                ORG     RESET_VECTOR            ; RESET Vector
                DW      RESET                   ; POR, ext. Reset
                END
  • Hi Andres,

    It will be difficult to help you with the information provided.

    •  When you say that it always "jumps to main", do you mean that you can't debug the bootloader at all?
    • I assume that you modified the linker file for the F2274 properly. Your output .txt file should look similar to this:

    @1000

    FF 3F F2 B2 20 00 02 24 30 40 00 F8 31 40 80 02

    <more lines>

    @F800

    03 43 D2 D3 22 00 B2 40 80 5A 20 01 D2 E3 21 00

    3F 43 1F 83 1F 53 1F 83 FC 23 F8 3F

    @FFFE

    02 10

    q

    Note that the "F800" can be different for the F2272 but the reset vector should point to the first instruction of the bootloader (in the case above=0x1002). And the bootloader must be placed in 0x1000.

    Check this link if you don't know how to generate a .txt file: http://processors.wiki.ti.com/index.php/Generating_and_Loading_MSP430_Binary_Files

    • In your project, make sure that you don't have the "Run to Main' option enabled in Options->Debugger
    • Make sure that Options->FET Debugger->Setup->Attach to Running Target is disabled
    • Make sure you are erasing and writing the whole info memory in Options->FET Debugger->Download

    • Make sure that P1.3 is OK in order to force the Bootloader
    • I'm not sure if you can see any activity on the SPI bus, but that code looks OK from a quick look. 
    • The only thing I notice in your code is that you are not initializing Addr (which apparently is used to get the addresses from SPI) and you are not incrementing rPoint (which is used to get out of the loop)

    Regards,

    Luis R

  • Hi Luis,

    I can  debug, but when the program reaches the 10CEE address  , go to main, in other ocasion  the jump address was 10C00, in the image you can see better. From the green colored line goes to main.

    I modified the linker file, similar as you share in the file above, is practically similar to the example in slaa450, because the size of the information memory is the same.

    This is my .txt

    @1000
    FF 3F F2 B2 20 00 02 24 30 40 00 80 31 40 00 06
    B2 40 80 5A 20 01 C2 43 56 00 F2 D0 31 00 1B 00
    F2 D0 41 00 19 00 F2 D0 40 00 1A 00 F2 D0 69 00
    60 00 F2 D0 80 00 61 00 E2 43 62 00 C2 43 63 00
    D2 C3 61 00 38 40 00 80 C8 43 00 00 38 90 00 FE
    03 34 38 50 00 02 F8 3F B2 40 02 10 FE FF 38 40
    00 80 B0 12 92 10 38 90 FE FF 06 24 D8 42 66 00
    00 00 18 53 15 53 F5 3F 80 43 A6 F0 E2 B3 03 00
    FD 27 C2 44 67 00 D2 B3 03 00 FD 27 D2 C3 03 00
    30 41 F2 D0 40 00 19 00 F2 C0 40 00 19 00 74 40
    03 00 B0 12 7C 10 74 40 FE 00 B0 12 7C 10 07 45
    87 10 04 47 B0 12 7C 10 44 45 B0 12 7C 10 74 40
    77 00 B0 12 7C 10 F2 C0 40 00 19 00 F2 D0 40 00
    19 00 30 41
    @8000
    03 43 D2 D3 22 00 B2 40 80 5A 20 01 D2 E3 21 00
    3F 43 1F 83 1F 53 1F 83 FC 23 F8 3F
    @FFFE
    02 10
    q

    The SPI read functions works fine, I used it with no problem, the only thing is that I don't know how to correct the clk bug, cause I can not go beyond the spi function. 

    I did all your suggestion but still not working.

    Thanks for responding so quickly.

    ANDRÉS FELIPE RODRÍGUEZ.

  • Hi Andres,

    From the screenshot, I can see that info-A is not being erased/written. Your .txt has code in this area, but you have 0xFFs which means that IAR is not writing this area.

    Try Options->FET Debugger->Download->Allow erase/write access to locked flash memory

    And Options->FET Debugger->Download->Erase main and Information memory

    Regards,

    Luis R

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