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MSP430FR5738 Oscillator fault

  No matter what I try, the oscillator fault reoccurs.  I have verified the 24 MHz xtal is ringing
(yes - using correct test methods).  The 5738 has two pins PJ.4 and PJ.5 for the xtal, so
I had top guess that meant the PJSEL had to be set for those bits - not mentioned anywhere.
Is that true?       Then, here's the startup code...

WDTCTL = WDTPW | WDTHOLD;        // Stop watchdog timer
    SFRIE1_L = 0;                    // no interrupts please
    init_Ports();                    // start out fresh - sets up XT1 pins
    PJSEL1 = 0;                        // PJ.4 and PJ.5 are the crystal XIN XOUT
    PJSEL0 = BIT4 | BIT5;           // select "tertiary function"
    CSCTL0 = 0xA500;                 // password to access clock system
    CSCTL1 = DCORSEL + DCOFSEL_3;    // Set DCO to 24 MHz
    CSCTL2 = 0;                      // set ACLK = XT1; SMCLK = XT1 MCLK = XT1
    CSCTL3 = 0;                      // set all dividers to one
    CSCTL4 = XT2OFF | XT1DRIVE_3 | XTS;        // max XT1 drive / high freq mode
    CSCTL6 = 0;
    CSCTL0_H = 0;                    // close out password

    for(x=0; x++>0; CSCTL5 &= ~XT1OFFG);

    while (SFRIFG1 & OFIFG);        // Test XT1 oscillator fault flag - Wait for XT1 to stabilize
          {      CSCTL5 &= ~XT1OFFG;        // Clear XT1 fault flag
                SFRIFG1 &= ~OFIFG;        // Clear XT1 oscillator fault interrupt flag
          }

It never gets out.  OFIFG stays set.  I can run on the DCO just fine - but I need the crystal for stability.
Has anybody got a clue as to what is wrong?     DK

  • Dennis Kodimer said:
    I had top guess

    You don’t need to guess only to read the Data Sheet! The Port Schematic’s part explains clearly how to setup.

  • Dennis Kodimer said:
    Has anybody got a clue as to what is wrong?

    Clue: An extra ; makes a big difference.

  • I fat-fingered that semicolon into the post. The actual code didn't have that mistake. The "guess" comment is superfluous - I don't guess.
    Used the TI sample programs -no joy. Because my firmware was almost identical the samples - and then modified to duplicate the samples,
    I concluded that the problem must be hardware. I have two boards doing the same thing. The only thing unusual about my hardware
    is that there's about 14 mm betwixt the crystal and the 5738 - somewhat long. Already tried different value load caps. There is 24 MHz ringing on the crystal itself (~ 1/2 Vpp) still the layout is all I have left to point at. So, I'm running on the DCO for now to finish the firmware
    qualification and will re-layout the circuit board later hoping that's the issue. I'll get back to this thread at that time. Thanks all.
  • "I had top guess that meant the PJSEL had to be set for those bits - not mentioned anywhere."

    From the users guide:
    The XT1 pins are shared with general-purpose I/O ports. At power up, the default operation is XT1, LF mode of operation. However, XT1 remains disabled until the ports shared with XT1 are configured for XT1 operation. The configuration of the shared I/O is determined by the PSEL bit associated with XIN and the XT1BYPASS bit. Setting the PSEL bit causes the XIN and XOUT ports to be configured for XT1 operation.
    If XT1BYPASS is also set, XT1 is configured for bypass mode of operation, and the oscillator associated with XT1 is powered down. In bypass mode of operation, XIN can accept an external clock input signal and XOUT is configured as a general-purpose I/O. The PSEL bit associated with XOUT is a don't care.

    The port pin schematics and truth table in the datasheet also tell the required settings.

    However, if the crystal is oscillating, you should be able to clear XT1OFFG and then OFIFG. (you say, OFIFG stays set - what about XT1OFFG?) If there were XT2 and it had a fault, XT2OFG had to be cleared too, but according to the users guide, this bit is read-only zero if there is no XT2 oscillator. You may try to clear it anyway.
  • The revised PWB layout was the key. The first layout had the 24 MHz Xtal at about 3/4" (1.2" line length without a ground plane and
    there were some some bends in the lines. Second layout pulled the crystal and load caps in snug - inside 3/8" to the FR5738 and
    - away she goes! That was the issue all along. First time (in dozens of designs) I've had any fussiness concerning the crystal layout.
    Might be peculiar to the FR series? Thanks for the support - greatly appreciated. It gets lonely doing 430 design out here in the desert.

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