See listing below of an attempt to use port mapping on the cc430F5137. After configuring the clock source to use the 26MHz radio crystal I attempt to map the PM_SMCLK to pins of Port3. Even following closely to the example code, cc430513x_PortMap_02.c, I am unable to get the device to behave. I use SMCLK simply for ease of observation. (I really want to move the UART Tx and Rx pins from Port1 to Port3.) Using the default mapping of SMCLK, I can see the clock appear on P3.7, but attempts to use the port mapping method fails.
What am I missing?
DE
void main (void){
WDTCTL = WDTPW + WDTHOLD; // Stop WD
// ---------------------------------------------------------
// Increase Vcore setting to level3 to support fsystem=26MHz
// (used by RF section) Change core voltage one level at a time...
SetVcoreUpLcl (0x01);
SetVcoreUpLcl (0x02);
SetVcoreUpLcl (0x03);
// ---------------------------------------------------------
// Clocks are configured in Bsp_SetClocks() in bsp_board.c
BSP_Init();
// ---------------------------------------------------------
// Here is our code for setting up to run from XT2. --Ray Keefe
// e2e.ti.com/.../1047345.aspx
// clear existing controls and use DCO for now
UCSCTL1 = DCORSEL_4 | DISMOD_L; // Frequency range setting w/o modulation
// set up for crystal oscillator running as high frequency XT2
UCSCTL2 = FLLN0_L; // Set FLL divider to 1
UCSCTL3 = SELREF_5; // Select XT2
UCSCTL5 = DIVS__2; // Divide the SMCLK by 2, want 13MHz
UCSCTL6 &= ~(XT2OFF); // Enable XT2 SLAU208m 5.2.5
UCSCTL6 &= ~(XT1DRIVE0); // set the correct drive level for 20MHz
UCSCTL6 |= XT1DRIVE1;
// ensure ACLK is not using XT1 or else the oscillator fault
// flag will remain set and the stabilization loop will never exit
// UCSCTL4 = SELM__XT2CLK | SELS__XT2CLK | SELA__XT2CLK;
// UCSCTL4 = SELM__DCOCLKDIV | SELS__DCOCLKDIV | SELA__DCOCLKDIV;
UCSCTL4 = SELM__REFOCLK | SELS__REFOCLK | SELA__REFOCLK;
_BIC_SR(OSCOFF); // turn off XT1 LF oscillator
// now to wait for the external crystal oscillator to start
do{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // oscillator fault interrupt flag, SFRIFG1.1
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
// oscillator started so we can use it now - safe mode means
// that DCO will take over if XTAL fails
UCSCTL4 = SELM__XT2CLK | SELS__XT2CLK | SELA__XT2CLK;
// Clear fault flags according to erratum
UCSCTL7 &= ~(DCOFFG + XT2OFFG + XT1LFOFFG + XT1HFOFFG + XT2OFFG);
// This works for our scenario which is no XT1 and ACLK, MCLK, SMCLK from XT2
// ---------------------------------------------------------
P3DIR |= BIT2 +BIT3 +BIT7; // dummy SMCLK outputs
__disable_interrupt(); // Disable Interrupts before altering
// Port Mapping registers
PMAPPWD = 0x02D52; // Enable Write-access to modify
// Port Mapping registers
// PMAPKEYID = PMAPPWD; // Enable Write-access to modify
// PMAPCTL = PMAPRECFG; // Allow reconfiguration during runtime
PMAPCTL |= PMAPRECFG; // Allow reconfiguration during runtime
// #endif
P3MAP2 = PM_TA1CCR0A; // simple to check with scope . . .
P3MAP3 = PM_SMCLK;
P3MAP7 = PM_SMCLK;
PMAPPWD = 0; // Disable Write-Access to modify port mapping registers
__enable_interrupt(); // Re-enable all interrupt
while(1);
} // close main()
// ---------------------------------------------------------
