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SPI slave , causes issue after some transactions - bit shifting

Hariprasad C R
Intellectual 485 points
Other Parts Discussed in Thread: MSP430F5529

I am using MSP430F5529 experimenters board which act as a SPI slave in MODE 0 (data toggled on falling edge and sampled at rising edge of clock). I have enabled both TX and RX interrupts for UCB state machine. SPI is working in 4 pin mode.

So I am able to do some transaction through the SPI but after some time, the data is not shifted out from the MSP slave properly , i can see a bit shifting in the SOMI line,,(probed using DSO). what might be causing this issue after successfull operation for some time ??

  • 0
    TI__Guru**** 202106 points
    Hariprasad,

    Can you please provide some o-scope or logic analyzer screen shots along with an explanation of what you expect vs. what you get out? Perhaps provide some SPI initialization code? How many transactions are successful before the bit shift occurs, and does it always occur at the same time? Can you confirm that the master and MSP430 are synchronized on their SPI communication settings (phase, polarity, character length, mode, etc)?

    Regards,
    Ryan
  • 0
    Guru 227245 points
    There is nearly an unlimited number of possible reasons. Knowing the exact signal on the bus would help (as noted) and knowing the code would be useful too, to narrow them down.

    There are some known errata, but they refer to modes with phase shift.

    Using 4-wire mode is usually not what people think ans only required in systems with multiple masters or multiple slaves and a master with tight timing.
    The STE pin will simply disable and enable the clock input and the data output of the slave. It will NOT reset the state machine to a byte boundary.
    Using STE, you can talk to a slave, stop mid.byte, talk to another slave, the continue with the first one. So in most cases, it is necessary to also connect the master's chip select to an I/O pin (with interrupt) and reset the USCI when CS is de-asserted. Else it is possible that master and slave get out of sync. After all, SPI is a clocked bit stream. Any organization above (grouping bits to bytes or whole telegrams) is a matter of the hgh-level code.

    btw: Mode 0 means UCCLKPL=1 and UCCLKPH=0 (this differs from the typical setup on other MCUs)

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