Same priority interrupts starts at simultaneously

Prakash Balagangatharan

Other Parts Discussed in Thread: MSP430F5335

I have quite confusion after going through the interrupt priority handling articles. My confusion is " as per the MSP architecture if one inteerupt occurs it won't process any other interrupt untill the complention of the particular ISR, say for an example if two same priority interrupts are occurs simultaneously meaans how the ISR will be executed? Is there any chance to miss any of the interrupt because both of them same priority? Is anyone faced such a scenario? Please give me some inputs to handle this kind of scenario.

Thanks in advance

over 8 years ago

0 Leo Bosch over 8 years ago

Guru 23000 points

It would be good if you could narrow down your question with a certain MSP430 MCU or MSP430 family, and which simultaneously interrupt you mean.

0 Prakash Balagangatharan over 8 years ago in reply to Leo Bosch

Expert 2440 points

I am using MSP40F5338 uC.

0 Prakash Balagangatharan over 8 years ago in reply to Prakash Balagangatharan

Expert 2440 points

I am trying to read the data from GPS receiver also PC through UART. I am using MSP430F5335. Have any one faced same scenario.

0 Clemens Ladisch over 8 years ago

Guru 244020 points

Every interrupt has its own interrupt flag (IFG) in some register.
When an interrupt occurs, its flag is set. When any interrupt flag is set, and GIE is enabled, the CPU will run the interrupt handler. (While the handler is running, GIE is cleared.)When the interrupt has been handled, its flag is cleared.

All these flags ensure that no interrupts get lost.

The interrupt priorities matter only when multiple interrupt flags are set at the same time (this typically happens only when GIE is disabled for a long time), then the CPU chooses the interrupt with the highest priority.

0 Prakash Balagangatharan over 8 years ago in reply to Clemens Ladisch

Expert 2440 points

Clemens Ladisch said:
The interrupt priorities matter only when multiple interrupt flags are set at the same time (this typically happens only when GIE is disabled for a long time), then the CPU chooses the interrupt with the highest priority.

If the occurred interrupts means interrupts which are in queue all same priority means how the uC take decision which interrupts to be executed?

Also if two interrupts (with same priority) occurs at the same time how it will executed?

0 Clemens Ladisch over 8 years ago in reply to Prakash Balagangatharan

Guru 244020 points

There are no different interrupts with the same priority.

If the same interrupt happens again before it is handled, the flag just stays set.

0 Tony Philipsson over 8 years ago in reply to Prakash Balagangatharan

Guru 12050 points

What "same priority"?, they all have different priority.

0 Michael Weber over 8 years ago in reply to Tony Philipsson

TI__Prodigy 335 points

Hi Prakash,

I think you question is related to the interrupt priority when multiple IRQs in a module happens (e.g. two IRQ on P1.x at the same time)?

In this case it's your decision how the IRQs will be handled.

When you check for example P1IFG-register you see all pending IRQ and you can select that one you want to handle.

If you use the P1IV-regsiter instead, you got that IRQ with the highest priority related to the module, because all Interrupt-Vector registers have their own priority ranking.

Best regards,

Michael

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Same priority interrupts starts at simultaneously