hello there i am interfacing nrf24l01+ with msp430g2553 at transmitter side and at receiver side. now my CSN pin is P1.4, CE is P1.3, CLK is P1.5, SIMO is P1.7, SOMI is p1.6. IRQ is P2.0. now i am transmitting 'r'. at receiver i am getting 'r'. but after that if i am transmitting 's'. i am receiving 'r'. so it is my problem. my codes are below.
// Transmitter side ///
#include <msp430.h>
#include "nrf24l01.h"
#include <stdio.h>
#define PAYLOAD_SIZE 5
void CE_LOW(void);
void CSN_HIGH (void);
void CSN_LOW (void);
void CE_HIGH(void);
unsigned char SPI_SendByte(unsigned char);
void Delay (unsigned long);
unsigned char SPI_Send_command_with_ADDR (unsigned char, unsigned char,
unsigned char);
unsigned char SPI_Send_command_without_ADDR (unsigned char, unsigned char);
unsigned char SPI_Send_command_without_ADDR_M (unsigned char, unsigned char,unsigned char);
void NRF_prepareForTransmit(void);
void nrf_read_all(void);
unsigned char RX_ADDRESS_P0[5] = {5,6,7,8,9};
unsigned char RX_ADDRESS_P1[5] = {0,1,2,3,4};
//WE CAN SET FOLLOWING BY PROVIDING LAST BYTE 5,6,7 & 8 IN CORROSPONDING REGISTER
// THAT IS RX_ADDRESS_P2[5]={0,1,2,3,5};
// THAT IS RX_ADDRESS_P3[5]={0,1,2,3,6};
// THAT IS RX_ADDRESS_P4[5]={0,1,2,3,7};
// THAT IS RX_ADDRESS_P5[5]={0,1,2,3,8};
unsigned char TX_ADDRESS[5] = {5,6,7,8,9};
unsigned char ADDRESS[5];
unsigned char a[5],b[5];
unsigned char r;
unsigned char in=0,status,flag=0,ccmd,aaddr,ddata_byte,ttemp=0X00,ccommand,status_temp,byte;
unsigned int i,counter=0;
unsigned char MST_Data,SLV_Data;
unsigned char temp;
long retransmited=0;
#define CSN_TIME 100
#define CE_HIGH_TIME 1000
// Nordic variables
unsigned char nrf_configuration,nrf_enable_auto_ack,nrf_enable_rxaddr,nrf_setup_aw_reg,nrf_setup_retr_reg;
unsigned char nrf_rf_ch_reg=0,nrf_rf_setup_reg,nrf_status_reg,nrf_observe_tx_reg;
unsigned char nrf_rx_pw_p0_reg,nrf_fifo_status_reg,nrf_cd_reg;
unsigned char nrf_rx_pw_p1_reg,nrf_rx_pw_p2_reg,nrf_rx_pw_p3_reg,nrf_rx_pw_p4_reg,nrf_rx_pw_p5_reg;
unsigned char nrf_pipe0_addr_reg[5];
unsigned char nrf_pipe1_addr_reg[5];
unsigned char nrf_pipe2_addr_reg;
unsigned char nrf_pipe3_addr_reg;
unsigned char nrf_pipe4_addr_reg;
unsigned char nrf_pipe5_addr_reg;
unsigned char nrf_tx_addr_reg[5];
void main()
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
// P1OUT |= 0x02; // Set P1.0 for LED
P2DIR = BIT3+BIT4+BIT5; // Set P1.1 for slave reset
P1DIR |= BIT0+BIT1+BIT2; // Set P1.0-2 to output direction
P1SEL |= BIT5+BIT6+BIT7;
P1SEL2 |= BIT5+BIT6+BIT7; // P4.4,5 option select
P1DIR |= BIT5+BIT7;
P1DIR &= ~BIT6;
P1DIR |= BIT3 | BIT4; // P4.1 (#CS) and P4.2 (CE) are outputs
P2DIR &= ~BIT0; // P2.0 (IRQ) is input
P2REN |= BIT0;
P2OUT |= BIT0;
P2IN |= BIT0;
//P2SEL |= BIT7; // P2.7 option select
//p4.0 = uca1clk, p4.4 = uca1simo , p4.5 = uca1miso
//P4.1= CSN, P4.2 = CE,
// P5SEL |= BIT1 | BIT2 | BIT3; // P5.1-3 SPI option select
// P5DIR |= BIT1 | BIT3; // P5.1 (MOSI) and P5.3 (CLK) are outputs
// P5DIR &= ~BIT2; // P5.2 (MISO) is input
// P5DIR |= BIT0 | BIT4; // P5.4 (#CS) and P5.0 (CE) are outputs
// P1DIR &= ~BIT6; // P1.6 (IRQ) is input
UCB0CTL1 |= UCSWRST; // **Put state machine in reset**
UCB0CTL0 |= UCMST+UCSYNC+UCCKPH+UCMSB; // 3-pin, 8-bit SPI master
// Initialize SPI interface
// master mode, data valid on rising edge, msb first(Because NRF24L01
//wants MSB First)
//UCB1CTL0 = UCCKPH + UCMST + UCMSB + UCSYNC;
UCB0CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC;
UCB0CTL1 |= UCSSEL_2; // SMCLK
// (4)
UCB0CTL1 &= ~UCSWRST;
// UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
for(i=5000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
// Disable CS
CSN_HIGH();
// Configure chip nRF24L01
// Discard transmission
CE_LOW();
/*
Delay(10000);
Delay(10000);
Delay(10000);
Delay(10000);
Delay(10000);
Delay(10000);
//Write CONFIG register (addres - 0x00)
//00011111 - CRC enable, power-up, RX
status = SPI_Send_command_with_ADDR(W_REGISTER,CONFIG_REG_ADDR, 0x02);
Delay(10000);
Delay(10000);
Delay(10000);
Delay(10000);
Delay(10000);
Delay(10000);
*/
//Flush tx buffer
/*
status = SPI_Send_command_without_ADDR(0xFF,0xFF);
if ((status & MAX_RT) != 0) // interrupt MAX_RT=1
{
//clear MAX_RT bit
status_temp = SPI_Send_command_with_ADDR(W_REGISTER,STATUS_ADDR,(status|MAX_RT));
//Flush TX FIFO
status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP);
}
if ((status & TX_DS) != 0)
{
// Clear TX_DS bit in status register
status_temp = SPI_Send_command_with_ADDR(W_REGISTER, STATUS_ADDR, (status|TX_DS));
}
// If TX full
if ((status & TX_FULL) != 0)
{
// Flush TX FIFO (in TX mode)
status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP);
}
status_temp = SPI_Send_command_without_ADDR(FLUSH_RX, NRF_NOP);
*/
NRF_prepareForTransmit();
CE_LOW();
//nrf_read_all();
byte=0;
while(1)
{
//IMPLEMENT CONTINUOUS TRANSMISSION
//FOR TRANSMISSION
//status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP);
// Send payload - send any data
for(in=0;in<PAYLOAD_SIZE;in++)
{
// a[in]='s';
if ( !(P2IN & BIT2) )
{ // If not (port one input AND bit3 (sw1))
//do_led( BIT6, 2000 ); // Turn on LED 2
P2OUT &= ~BIT4;
a[in]='r';
//P1OUT &= ~ BIT6;
}
else
{
P2OUT |= BIT4;
a[in]='s';
// P1OUT |= BIT6; // Otherwise...
}
//do_led( BIT0, 100 ); // Turn on LED 1
}
if (a[0] == 's')
{ P2OUT |= BIT3;
// P2OUT &= ~BIT3;
}
else
{
P2OUT &= ~BIT3;
//P2OUT |= BIT3;
}
// m=31;
//status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP); //test code
status = SPI_Send_command_without_ADDR_M (W_TX_PAYLOAD, byte,PAYLOAD_SIZE);
Delay(100);
// Pulse for CE -> starts the transmission.
CE_HIGH();
Delay(30);
CE_LOW();
Delay(30);
// while (P2IN & BIT0); // wait until transmitted to air
//Delay(10000);
// Read STATUS register
status = SPI_Send_command_without_ADDR(NRF_NOP, NRF_NOP);
// if exceed number of transmision packets
if ((status & MAX_RT) != 0)
{
// Clear MAX_RT bit in status register
status_temp = SPI_Send_command_with_ADDR(W_REGISTER, STATUS_ADDR,(status|MAX_RT));
// No communication event here
retransmited++;
// Flush TX FIFO (in TX mode)
status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP); //test code
}
// If packet sent on TX
if ((status & TX_DS) != 0)
{
// Clear TX_DS bit in status register
status_temp = SPI_Send_command_with_ADDR(W_REGISTER, STATUS_ADDR, (status|TX_DS));
counter++;
}
// If TX full
if ((status & TX_FULL) != 0)
{
// Flush TX FIFO (in TX mode)
status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP);
}
}
}
unsigned char SPI_SendByte(unsigned char data)
{
UCB0TXBUF = data;
// wait for TX
while (!(IFG2 & UCB0TXIFG));
return UCB0RXBUF;
}
void Delay (unsigned long a)
{
while (--a != 0);
}
void CSN_HIGH (void)
{
P1OUT |= BIT4; // P4.1 HIGH
}
void CSN_LOW (void)
{
Delay (CSN_TIME);
P1OUT &= ~BIT4; // P4.1 LOW
}
void CE_HIGH(void)
{
P1OUT |= BIT3; // P4.2 HIGH
Delay (CE_HIGH_TIME);
}
void CE_LOW(void)
{
P1OUT &= ~BIT3; // P4.2 LOW
}
//THIS ROUTINE IS FOR READING AND WRITING OF LAST 6 INSTRUCTION REGISTERS
unsigned char SPI_Send_command_without_ADDR (unsigned char cmd, unsigned char data_byte)
{
unsigned char temp = 0;
CSN_LOW();
if (cmd == R_RX_PAYLOAD)//USED WHEN NRF IS IN TXD MODE
{
status = SPI_SendByte(cmd);
temp = SPI_SendByte(NRF_NOP);//DUMMY BYTES
CSN_HIGH();
return temp;
}
if (cmd == W_TX_PAYLOAD)//USED WHEN NRF IS IN TXD MODE
{
status = SPI_SendByte(cmd);
SPI_SendByte(data_byte);//SENDING THE ACTUAL PAYLOAD/DATA FOR TRANSMISSION
CSN_HIGH();
return status;
}
status = SPI_SendByte(cmd);
CSN_HIGH();
return status;
}
//THIS ROUTINE IS FOR READING AND WRITING OF LAST 6 INSTRUCTION REGISTERS
//THIS ROUTINE IS FOR READING AND WRITING OF FIRST 2 INSTRUCTION REGISTERS
unsigned char SPI_Send_command_with_ADDR (unsigned char cmd, unsigned char addr, unsigned char data_byte)
{
unsigned char temp,command = 0;
int j, k;
command = (cmd << 5) | addr;
CSN_LOW();
if (cmd == R_REGISTER)
{
if (addr == RX_ADDR_P0 || addr == RX_ADDR_P1 || addr == TX_ADDR)
{
status = SPI_SendByte(command);
for (k = 0; k < 5; k++)
{
ADDRESS[k] = SPI_SendByte(NRF_NOP);
}
CSN_HIGH();
return status;
}
else
{
status = SPI_SendByte(command);
temp = SPI_SendByte(NRF_NOP);
CSN_HIGH();
return temp;
}
}
if (cmd == W_REGISTER)
{
if (addr == RX_ADDR_P0)
{
status = SPI_SendByte(command);
for (j = 0; j < 5; j++)
{
temp = RX_ADDRESS_P0[j];
SPI_SendByte(temp);
}
CSN_HIGH();
return status;
}
if (addr == RX_ADDR_P1)
{
status = SPI_SendByte(command);
for (j = 0; j < 5;j++)
{
temp = RX_ADDRESS_P1[j];
SPI_SendByte(temp);
}
CSN_HIGH();
return status;
}
if (addr == TX_ADDR)
{
status = SPI_SendByte(command);
for (j = 0; j < 5;j++)
{
temp = TX_ADDRESS[j];
SPI_SendByte(temp);
}
CSN_HIGH();
return status;
}
else
{
temp = SPI_SendByte(command);
SPI_SendByte(data_byte);
CSN_HIGH();
return temp;
}
}
return 1;
}
unsigned char SPI_Send_command_without_ADDR_M (unsigned char cmd, unsigned char data_byte, unsigned char mm)
{
unsigned char temp = 0,rm=0,t=0;
CSN_LOW();
if (cmd == R_RX_PAYLOAD)//USED WHEN NRF IS IN RXD MODE
{
status = SPI_SendByte(cmd);
while(mm!=rm)//GO ON RECEIVING PAYLOAD UNTIL ALL ARE RECEIVED
{
temp = SPI_SendByte(NRF_NOP);//DUMMY BYTES
b[rm]=temp;
rm++;
}
CSN_HIGH();
return temp;
}
if (cmd == W_TX_PAYLOAD)//USED WHEN NRF IS IN TXD MODE
{
status = SPI_SendByte(cmd);
while(mm>0)
{
SPI_SendByte(a[t]);//SENDING THE ACTUAL PAYLOAD/DATA FOR TRANSMISSION
t++;
mm--;
}
CSN_HIGH();
return status;
}
status = SPI_SendByte(cmd);
CSN_HIGH();
return status;
}
void nrf_read_all(void)
{
nrf_configuration = SPI_Send_command_with_ADDR(R_REGISTER,CONFIG_REG_ADDR ,0xFF);
nrf_enable_auto_ack = SPI_Send_command_with_ADDR(R_REGISTER,ENAA ,0xFF);
nrf_enable_rxaddr = SPI_Send_command_with_ADDR(R_REGISTER, EN_RXADDR,0xFF);
nrf_setup_aw_reg = SPI_Send_command_with_ADDR(R_REGISTER,SETUP_AW ,0xFF);
nrf_setup_retr_reg = SPI_Send_command_with_ADDR(R_REGISTER,SETUP_RETR ,0xFF);
nrf_rf_ch_reg = SPI_Send_command_with_ADDR(R_REGISTER,RF_CH ,0xFF);
nrf_rf_setup_reg = SPI_Send_command_with_ADDR(R_REGISTER,RF_SETUP ,0xFF);
nrf_status_reg = SPI_Send_command_with_ADDR(R_REGISTER,STATUS_ADDR ,0xFF);
nrf_observe_tx_reg= SPI_Send_command_with_ADDR(R_REGISTER,OBSERVE_TX ,0xFF);
nrf_cd_reg = SPI_Send_command_with_ADDR(R_REGISTER, CD ,0xFF);
status_temp = SPI_Send_command_with_ADDR(R_REGISTER,TX_ADDR ,0xFF);
for (i=0;i<5;i++)
{
nrf_tx_addr_reg[i]=ADDRESS[i];
}
status_temp = SPI_Send_command_with_ADDR(R_REGISTER, RX_ADDR_P0,0xFF);
for (i=0;i<5;i++)
{
nrf_pipe0_addr_reg[i]=ADDRESS[i];
}
status_temp = SPI_Send_command_with_ADDR(R_REGISTER, RX_ADDR_P1,0xFF);
for (i=0;i<5;i++)
{
nrf_pipe1_addr_reg[i]=ADDRESS[i];
}
status_temp = SPI_Send_command_with_ADDR(R_REGISTER, RX_ADDR_P2,0xFF);
nrf_pipe2_addr_reg = ADDRESS[0];
status_temp = SPI_Send_command_with_ADDR(R_REGISTER,RX_ADDR_P3 ,0xFF);
nrf_pipe3_addr_reg = ADDRESS[0];
status_temp = SPI_Send_command_with_ADDR(R_REGISTER,RX_ADDR_P4,0xFF);
nrf_pipe4_addr_reg = ADDRESS[0];
status_temp= SPI_Send_command_with_ADDR(R_REGISTER,RX_ADDR_P5,0xFF);
nrf_pipe5_addr_reg = ADDRESS[0];
nrf_rx_pw_p0_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P0 ,0xFF);
nrf_rx_pw_p1_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P1 ,0xFF);
nrf_rx_pw_p2_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P2 ,0xFF);
nrf_rx_pw_p3_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P3 ,0xFF);
nrf_rx_pw_p4_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P4 ,0xFF);
nrf_rx_pw_p5_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P5 ,0xFF);
nrf_fifo_status_reg= SPI_Send_command_with_ADDR(R_REGISTER,FIFO_STATUS ,0xFF);
}
void NRF_prepareForTransmit(void)
{
// Setting for TX device
//Write CONFIG register -> 00011110 - CRC enable, power-up, TX
status = SPI_Send_command_with_ADDR(W_REGISTER, CONFIG_REG_ADDR, 0x1E);
Delay(50000);
Delay(50000);
Delay(50000);
Delay(50000);
Delay(50000);
Delay(50000);
status = SPI_Send_command_with_ADDR(W_REGISTER, ENAA, 0X01);
status = SPI_Send_command_with_ADDR(W_REGISTER, EN_RXADDR, ENRXP0);
status = SPI_Send_command_with_ADDR(W_REGISTER, SETUP_AW, 0X03);
status = SPI_Send_command_with_ADDR(W_REGISTER, RF_CH, 0x02);
status = SPI_Send_command_with_ADDR(W_REGISTER, RF_SETUP, 0x07);
//Write RX_ADDR_P0 register -> Set receive address data Pipe0 -> address in RX_ADDRESS_P0 array
status = SPI_Send_command_with_ADDR(W_REGISTER, RX_ADDR_P0, NRF_NOP);
//Write TX_ADDR register -> Transmit address. Used for a PTX device only. Address in TX_ADDRESS array
status = SPI_Send_command_with_ADDR(W_REGISTER, TX_ADDR, NRF_NOP);
//Write RX_PW_P0 register -> Set number of bytes in RX payload in data pipe0
status = SPI_Send_command_with_ADDR(W_REGISTER, RX_PW_P0, PAYLOAD_SIZE);
status = SPI_Send_command_with_ADDR(W_REGISTER, SETUP_RETR, 0x2F);
}
receiver code
#include <msp430.h>
#include "nrf24l01.h"
#include <stdio.h>
#define PAYLOAD_SIZE 5
void NRF_prepareForReceive(void);
void CE_LOW(void);
void CSN_HIGH (void);
void CSN_LOW (void);
void CE_HIGH(void);
void Delay (unsigned long);
unsigned char SPI_SendByte(unsigned char);
void nrf_read_all(void);
unsigned char SPI_Send_command_with_ADDR (unsigned char, unsigned char,
unsigned char);
unsigned char SPI_Send_command_without_ADDR (unsigned char, unsigned char);
unsigned char SPI_Send_command_without_ADDR_M (unsigned char, unsigned char,unsigned char);
unsigned char a[2],b[PAYLOAD_SIZE];
unsigned char RX_ADDRESS_P0[5] = {5,6,7,8,9};
unsigned char RX_ADDRESS_P1[5] = {0,1,2,3,4};
//WE CAN SET FOLLOWING BY PROVIDING LAST BYTE 5,6,7 & 8 IN CORROSPONDING REGISTER
// THAT IS RX_ADDRESS_P2[5]={0,1,2,3,5};
// THAT IS RX_ADDRESS_P3[5]={0,1,2,3,6};
// THAT IS RX_ADDRESS_P4[5]={0,1,2,3,7};
// THAT IS RX_ADDRESS_P5[5]={0,1,2,3,8};
unsigned char TX_ADDRESS[5] = {5,6,7,8,9};
unsigned char ADDRESS[5];
unsigned char status,ccmd,aaddr,ddata_byte,ttemp=0X00,ccommand,status_temp,byte,payload;
unsigned int i,ii,count=0,counter=2;
unsigned char MST_Data,SLV_Data;
unsigned char temp;
#define CSN_TIME 10
#define CE_HIGH_TIME 30
// Nordic variables
unsigned char nrf_configuration,nrf_enable_auto_ack,nrf_enable_rxaddr,nrf_setup_aw_reg,nrf_setup_retr_reg;
unsigned char nrf_rf_ch_reg=0,nrf_rf_setup_reg,nrf_status_reg,nrf_observe_tx_reg;
unsigned char nrf_rx_pw_p0_reg,nrf_fifo_status_reg,nrf_cd_reg;
unsigned char nrf_rx_pw_p1_reg,nrf_rx_pw_p2_reg,nrf_rx_pw_p3_reg,nrf_rx_pw_p4_reg,nrf_rx_pw_p5_reg;
unsigned char nrf_pipe0_addr_reg[5];
unsigned char nrf_pipe1_addr_reg[5];
unsigned char nrf_pipe2_addr_reg;
unsigned char nrf_pipe3_addr_reg;
unsigned char nrf_pipe4_addr_reg;
unsigned char nrf_pipe5_addr_reg;
unsigned char nrf_tx_addr_reg[5];
unsigned char array[256],ib=0;
unsigned int ia=0;
void main()
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
P1OUT |= 0x02; // Set P1.0 for LED
// Set P1.1 for slave reset
P1DIR |= 0x03;
P2DIR |= BIT2;
// P1DIR |= BIT1;// Set P1.0-2 to output direction
P1SEL |= BIT5+BIT6+BIT7; // P4.4,5 option select
P1SEL2 |= BIT5+BIT6+BIT7;
P1DIR |= BIT5+BIT7;
P1DIR &= ~BIT6;
P1DIR |= BIT3 | BIT4; // P4.1 (#CS) and P4.2 (CE) are outputs
P2DIR &= ~BIT0; // P2.0 (IRQ) is input
P2REN |= BIT0;
P2OUT |= BIT0;
P2IN |= BIT0;
// UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
// UCA1CTL0 |= UCMST+UCSYNC+UCCKPH+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
// UCA1CTL1 |= UCSSEL_2; // SMCLK
// UCA1BR0 = 0x02; // /2
// UCA1BR1 = 0; //
// UCA1MCTL = 0; // No modulation
// UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
// UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt
UCB0CTL1 |= UCSWRST; // **Put state machine in reset**
UCB0CTL0 |= UCMST+UCSYNC+UCCKPH+UCMSB; // 3-pin, 8-bit SPI master
// Initialize SPI interface
// master mode, data valid on rising edge, msb first(Because NRF24L01
//wants MSB First)
//UCB1CTL0 = UCCKPH + UCMST + UCMSB + UCSYNC;
UCB0CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC;
UCB0CTL1 |= UCSSEL_2; // SMCLK
// (4)
UCB0CTL1 &= ~UCSWRST;
for(i=50000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
for(i=50000;i>0;i--); // Wait for slave to initialize
// P6DIR=0X80; //ADC (P6.2) AS INPUT AND DAC (P6.7) AS OUTPUT
// P6SEL=0X84; //P6.2 = A2 AS ADC 0, P6.7 = DAC1
// DAC12_1CTL = DAC12IR + DAC12AMP_5 + DAC12ENC ;// Internal ref gain 1
// ADC12CTL0 = REF2_5V + REFON ; // MAKE REFERENCE ON FOR DAC
// Disable CS
CSN_HIGH();
// Configure chip nRF24L01
// Discard transmission
CE_LOW();
//Flush tx buffer
/*
status = SPI_Send_command_without_ADDR(0xFF,0xFF);
if ((status & MAX_RT) != 0) // interrupt MAX_RT=1
{
//clear MAX_RT bit
status_temp = SPI_Send_command_with_ADDR(W_REGISTER,STATUS_ADDR,(status|MAX_RT));
//Flush TX FIFO
status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP);
}
if ((status & TX_DS) != 0)
{
// Clear TX_DS bit in status register
status_temp = SPI_Send_command_with_ADDR(W_REGISTER, STATUS_ADDR, (status|TX_DS));
}
// If TX full
if ((status & TX_FULL) != 0)
{
// Flush TX FIFO (in TX mode)
status_temp = SPI_Send_command_without_ADDR(FLUSH_TX, NRF_NOP);
}
status_temp = SPI_Send_command_without_ADDR(FLUSH_RX, NRF_NOP);
*/
//FOLLOWING WILL BE REQUIRED FOR RECEIVER FILE !!!
NRF_prepareForReceive ();
//nrf_read_all();
while(1)
{
//FOR RECEPTION MAKE CE HIGH
CE_HIGH ();
if (IRQ ()) // check interrupt line of nRF24L01...
{
// Read STATUS status register
status = SPI_Send_command_without_ADDR(NRF_NOP, NRF_NOP);
// Set high when new data arrives RX FIFO
if ((status & RX_DR) != 0)
{
// Chip enable low
CE_LOW();
//Read payload data
//m=31;
payload = SPI_Send_command_without_ADDR_M(R_RX_PAYLOAD, NRF_NOP,PAYLOAD_SIZE);
ii++;
//COMBINE b[0] and b[1] INTO A SINGLE 12 BIT NO AND GIVE TO DAC12
temp = b[1];
temp = temp <<8;
temp = temp &0xFF00;
temp = temp | b[0];
// DAC12_1DAT = temp ;
if (b[0] == 's')
{
P2OUT |= BIT2;
}
else
{
P2OUT &= ~BIT2;
}
// Clear RX_DR bit in status register
// *byte = payload;
// Flush RX FIFO
status_temp = SPI_Send_command_without_ADDR(FLUSH_RX, NRF_NOP); //XXX test code
}
}
}//END OF WHILE
}//END OF MAIN
unsigned char SPI_SendByte(unsigned char data)
{
//while ((UCA1IFG & UCTXIFG) == 0); // wait while not ready / for RX
//UCA1TXBUF = data; // write
//while ((UCA1IFG & UCRXIFG) == 0); // wait for RX buffer (full)
//return (UCA1RXBUF);
UCB0TXBUF = data;
// wait for TX
while (!(IFG2 & UCB0TXIFG));
return UCB0RXBUF;
}
void Delay (unsigned long a)
{
while (--a != 0);
}
void CSN_HIGH (void)
{
P1OUT |= BIT4; // P4.1 HIGH
}
void CSN_LOW (void)
{
Delay (CSN_TIME);
P1OUT &= ~BIT4; // P4.1 LOW
}
void CE_HIGH(void)
{
P1OUT |= BIT3; // P4.2 HIGH
Delay (CE_HIGH_TIME);
}
void CE_LOW(void)
{
P1OUT &= ~BIT3; // P4.2 LOW
}
//THIS ROUTINE IS FOR READING AND WRITING OF LAST 6 INSTRUCTION REGISTERS
unsigned char SPI_Send_command_without_ADDR (unsigned char cmd, unsigned char data_byte)
{
unsigned char temp = 0;
CSN_LOW();
if (cmd == R_RX_PAYLOAD)//USED WHEN NRF IS IN TXD MODE
{
status = SPI_SendByte(cmd);
temp = SPI_SendByte(NRF_NOP);//DUMMY BYTES
CSN_HIGH();
return temp;
}
if (cmd == W_TX_PAYLOAD)//USED WHEN NRF IS IN TXD MODE
{
status = SPI_SendByte(cmd);
SPI_SendByte(data_byte);//SENDING THE ACTUAL PAYLOAD/DATA FOR TRANSMISSION
CSN_HIGH();
return status;
}
status = SPI_SendByte(cmd);
CSN_HIGH();
return status;
}
//THIS ROUTINE IS FOR READING AND WRITING OF LAST 6 INSTRUCTION REGISTERS
unsigned char SPI_Send_command_without_ADDR_M (unsigned char cmd, unsigned char data_byte, unsigned char mm)
{
unsigned char temp = 0,rm=0;
CSN_LOW();
if (cmd == R_RX_PAYLOAD)//USED WHEN NRF IS IN RXD MODE
{
status = SPI_SendByte(cmd);
while(mm!=rm)//GO ON RECEIVING PAYLOAD UNTIL ALL ARE RECEIVED
{
b[rm] = SPI_SendByte(NRF_NOP);//DUMMY BYTES
array[ib++]=b[rm];
if(ib==255)
ia++;
rm++;
}
CSN_HIGH();
return temp;
}
if (cmd == W_TX_PAYLOAD)//USED WHEN NRF IS IN TXD MODE
{
status = SPI_SendByte(cmd);
while(mm>0)
{
SPI_SendByte(data_byte);//SENDING THE ACTUAL PAYLOAD/DATA FOR TRANSMISSION
mm--;
}
CSN_HIGH();
return status;
}
status = SPI_SendByte(cmd);
CSN_HIGH();
return status;
}
//THIS ROUTINE IS FOR READING AND WRITING OF FIRST 2 INSTRUCTION REGISTERS
unsigned char SPI_Send_command_with_ADDR (unsigned char cmd, unsigned char addr,
unsigned char data_byte)
{
unsigned char temp,command = 0;
int j, k;
command = (cmd << 5) | addr;
CSN_LOW();
if (cmd == R_REGISTER)
{
if (addr == RX_ADDR_P0 || addr == RX_ADDR_P1 || addr == TX_ADDR)
{
status = SPI_SendByte(command);
for (k = 0; k < 5; k++)
{
ADDRESS[k] = SPI_SendByte(NRF_NOP);
}
CSN_HIGH();
return status;
}
else
{
status = SPI_SendByte(command);
temp = SPI_SendByte(NRF_NOP);
CSN_HIGH();
return temp;
}
}
if (cmd == W_REGISTER)
{
if (addr == RX_ADDR_P0)
{
status = SPI_SendByte(command);
for (j = 0; j < 5; j++)
{
temp = RX_ADDRESS_P0[j];
SPI_SendByte(temp);
}
CSN_HIGH();
return status;
}
if (addr == RX_ADDR_P1)
{
status = SPI_SendByte(command);
for (j = 0; j < 5;j++)
{
temp = RX_ADDRESS_P1[j];
SPI_SendByte(temp);
}
CSN_HIGH();
return status;
}
if (addr == TX_ADDR)
{
status = SPI_SendByte(command);
for (j = 0; j < 5;j++)
{
temp = TX_ADDRESS[j];
SPI_SendByte(temp);
}
CSN_HIGH();
return status;
}
else
{
temp = SPI_SendByte(command);
SPI_SendByte(data_byte);
CSN_HIGH();
return temp;
}
}
return 1;
}
void nrf_read_all(void)
{
nrf_configuration = SPI_Send_command_with_ADDR(R_REGISTER,CONFIG_REG_ADDR ,0xFF);
nrf_enable_auto_ack = SPI_Send_command_with_ADDR(R_REGISTER,ENAA ,0xFF);
nrf_enable_rxaddr = SPI_Send_command_with_ADDR(R_REGISTER, EN_RXADDR,0xFF);
nrf_setup_aw_reg = SPI_Send_command_with_ADDR(R_REGISTER,SETUP_AW ,0xFF);
nrf_setup_retr_reg = SPI_Send_command_with_ADDR(R_REGISTER,SETUP_RETR ,0xFF);
nrf_rf_ch_reg = SPI_Send_command_with_ADDR(R_REGISTER,RF_CH ,0xFF);
nrf_rf_setup_reg = SPI_Send_command_with_ADDR(R_REGISTER,RF_SETUP ,0xFF);
nrf_status_reg = SPI_Send_command_with_ADDR(R_REGISTER,STATUS_ADDR ,0xFF);
nrf_observe_tx_reg= SPI_Send_command_with_ADDR(R_REGISTER,OBSERVE_TX ,0xFF);
nrf_cd_reg = SPI_Send_command_with_ADDR(R_REGISTER, CD ,0xFF);
status_temp = SPI_Send_command_with_ADDR(R_REGISTER,TX_ADDR ,0xFF);
for (i=0;i<5;i++)
{
nrf_tx_addr_reg[i]=ADDRESS[i];
}
status_temp = SPI_Send_command_with_ADDR(R_REGISTER, RX_ADDR_P0,0xFF);
for (i=0;i<5;i++)
{
nrf_pipe0_addr_reg[i]=ADDRESS[i];
}
status_temp = SPI_Send_command_with_ADDR(R_REGISTER, RX_ADDR_P1,0xFF);
for (i=0;i<5;i++)
{
nrf_pipe1_addr_reg[i]=ADDRESS[i];
}
status_temp = SPI_Send_command_with_ADDR(R_REGISTER, RX_ADDR_P2,0xFF);
nrf_pipe2_addr_reg = ADDRESS[0];
status_temp = SPI_Send_command_with_ADDR(R_REGISTER,RX_ADDR_P3 ,0xFF);
nrf_pipe3_addr_reg = ADDRESS[0];
status_temp = SPI_Send_command_with_ADDR(R_REGISTER,RX_ADDR_P4,0xFF);
nrf_pipe4_addr_reg = ADDRESS[0];
status_temp= SPI_Send_command_with_ADDR(R_REGISTER,RX_ADDR_P5,0xFF);
nrf_pipe5_addr_reg = ADDRESS[0];
nrf_rx_pw_p0_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P0 ,0xFF);
nrf_rx_pw_p1_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P1 ,0xFF);
nrf_rx_pw_p2_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P2 ,0xFF);
nrf_rx_pw_p3_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P3 ,0xFF);
nrf_rx_pw_p4_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P4 ,0xFF);
nrf_rx_pw_p5_reg= SPI_Send_command_with_ADDR(R_REGISTER,RX_PW_P5 ,0xFF);
nrf_fifo_status_reg= SPI_Send_command_with_ADDR(R_REGISTER,FIFO_STATUS ,0xFF);
}
void NRF_prepareForReceive(void)
{
//Write CONFIG register (addres - 0x00)
//00011111 - CRC enable, power-up, RX
status = SPI_Send_command_with_ADDR(W_REGISTER,CONFIG_REG_ADDR, 0x1F);
Delay(50000);
Delay(50000);
Delay(50000);
Delay(50000);
Delay(50000);
Delay(50000);
status = SPI_Send_command_with_ADDR(W_REGISTER, ENAA, 0X01);
status = SPI_Send_command_with_ADDR(W_REGISTER, EN_RXADDR, ENRXP0);
status = SPI_Send_command_with_ADDR(W_REGISTER, SETUP_AW, 0X03);
status = SPI_Send_command_with_ADDR(W_REGISTER, RF_CH, 0x02);
status = SPI_Send_command_with_ADDR(W_REGISTER, RF_SETUP, 0x07);
//Write RX_ADDR_P0 register -> Set receive address data Pipe0 -> address in RX_ADDRESS_P0 array
status = SPI_Send_command_with_ADDR(W_REGISTER, RX_ADDR_P0, NRF_NOP);
//Write TX_ADDR register -> Transmit address. Used for a PTX device only. Address in TX_ADDRESS array
status = SPI_Send_command_with_ADDR(W_REGISTER, TX_ADDR, NRF_NOP);
//Write RX_PW_P1 register -> Set number of bytes in RX payload in data pipe1 -> 1 byte
status = SPI_Send_command_with_ADDR(W_REGISTER, RX_PW_P0, PAYLOAD_SIZE);
//Write RX_PW_P1 register -> Set number of bytes in RX payload in data pipe1 -> 1 byte
status = SPI_Send_command_with_ADDR(W_REGISTER, RX_PW_P1, PAYLOAD_SIZE);
status = SPI_Send_command_with_ADDR(W_REGISTER, SETUP_RETR, 0x2F);
}
can you give me solution???
