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slave reset in spi interface

Other Parts Discussed in Thread: MSP430G2553

hello there! i am communicating two msp430g2553 using two nrf24lo+. when i transmit 'a', receiver gets 'a'. then if i transmit 'b'. receiver does not get 'b'. if i push both reset switch. then slave receives 'b'. can you tell me how to reset using software. i am using this routine for spi


UCB0CTL0 |= UCMST+UCSYNC+UCCKPH+UCMSB; // 3-pin, 8-bit SPI master

// Initialize SPI interface
// master mode, data valid on rising edge, msb first(Because NRF24L01
//wants MSB First)
//UCB1CTL0 = UCCKPH + UCMST + UCMSB + UCSYNC;

UCB0CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC;
UCB0CTL1 |= UCSSEL_2; // SMCLK

// (4)
UCB0CTL1 &= ~UCSWRST;

 

  • Hello Rushin,

    Setting the UCSWRST bit inside of the UCB0CTL1 register holds the USCI logic in a reset state. Generally the USCI logic is held in reset (UCB0CTL1 |= UCSWRST;) while the registers are being initialized which I do not see in your code snippet and could explain the errors you are seeing. Otherwise the register initialization seems to be correct concerning clock polarity and phase in regards to the nRF24L01+ datasheet.

    Regards,
    Ryan

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