Grace 3.10.0.82 BUG for MSP430FR5969

Hello and thank you for your answer,

but I think this is not true. According to the documentation CCR1 and CCR2 are allowed in Interval mode - for example "16.2.3.3 Use of Continuous Mode". Here is another document describing the benefits of the rest CCRx registers - Multiple Time Bases on a Single MSP430™ Timer Module.

I've prepared a simple test code which demonstrate the usefulness of CCR1 and CCR2 in Up Mode. The code generates three frequencies which are out of phase by a fixed amount. The first is the main frequency, the second is out of phase by 76%(-43.2°) and the third is out of phase by 12%(-158.4°). This is easily seen on an oscilloscope.

Please, let me know what you think.

#include "driverlib.h"

#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR_HOOK(void)
{
		P1OUT ^=  BIT3;
}

#pragma vector=TIMER0_A1_VECTOR
__interrupt void TIMER0_A1_ISR_HOOK(void)
{
	switch (_even_in_range(TA0IV, TA0IV_TACCR2))
	{
		case TA0IV_TACCR1:
			P1OUT ^=  BIT4;
			break;
		case TA0IV_TACCR2:
			P1OUT ^=  BIT5;
			break;
	}
}

int main(void)
{
	WDT_A_hold(WDT_A_BASE);

	PMM_unlockLPM5();

	P1DIR = BIT3 | BIT4 | BIT5;

	CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
	CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8);
	CS_initClockSignal(CS_ACLK, CS_VLOCLK_SELECT, CS_CLOCK_DIVIDER_1);
	CS_setDCOFreq(CS_DCORSEL_0, CS_DCOFSEL_6);
	CS_clearAllOscFlagsWithTimeout(100000);
	CS_disableClockRequest(CS_MCLK);
	CS_disableClockRequest(CS_SMCLK);
	CS_disableClockRequest(CS_ACLK);

	Timer_A_initUpModeParam initUpParam = { 0 };
	initUpParam.clockSource = TIMER_A_CLOCKSOURCE_ACLK;
	initUpParam.clockSourceDivider = TIMER_A_CLOCKSOURCE_DIVIDER_1;
	initUpParam.timerInterruptEnable_TAIE = TIMER_A_TAIE_INTERRUPT_DISABLE;
	initUpParam.timerClear = TIMER_A_SKIP_CLEAR;
	initUpParam.startTimer = false;

	Timer_A_initUpMode(TIMER_A0_BASE, &initUpParam);
	Timer_A_enableCaptureCompareInterrupt(TIMER_A0_BASE, TIMER_A_CAPTURECOMPARE_REGISTER_0);
	Timer_A_enableCaptureCompareInterrupt(TIMER_A0_BASE, TIMER_A_CAPTURECOMPARE_REGISTER_1);
	Timer_A_enableCaptureCompareInterrupt(TIMER_A0_BASE, TIMER_A_CAPTURECOMPARE_REGISTER_2);

	Timer_A_setCompareValue(TIMER_A0_BASE, TIMER_A_CAPTURECOMPARE_REGISTER_0, 100);
	Timer_A_setCompareValue(TIMER_A0_BASE, TIMER_A_CAPTURECOMPARE_REGISTER_1, 76);
	Timer_A_setCompareValue(TIMER_A0_BASE, TIMER_A_CAPTURECOMPARE_REGISTER_2, 12);

	Timer_A_startCounter(TIMER_A0_BASE, TIMER_A_UP_MODE);

	__bis_SR_register(GIE);

	while (1)
	{

	}
}

This is the 12% frequency.

This is the 76% frequency.