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MSP430F6746 Erratasheet: USCI37

Other Parts Discussed in Thread: MSP430F6746
Hi all,
Thank you always for everything.
 
I have questions about USCI37 of MSP430F6746 Erratasheet.
 
1)When this bug occurs, Is the Bus Busy bit setting?
2) The workaround is as follow.
     (1) Execute two consecutive reads of RXBUF, if tSCL > 4 x tIFCLK
What is the tIFCLK
I think tIFCLK is feUSCI(eUSCI input clock frequency).
 
Best Regards,
Taka
  • Hello Taka,

    The Busy Bit should work as normal and is independent to this bug. As for tIFCLK, you are right to assume this is the input clock frequency to the eUSCI module. Thank you for bringing up that this is not clear in the errata description. I will work on attempting to get this changed in order to clarify the workaround.

    Regards,
    JH
  • Hi Jace-san.

    Thank you for your kindly reply. 

    I understood tIFCLK. 

    Please let me ask an additional question about the Bus Busy.

    I understood the Busy Bit should work as normal and is independent to this bug. 

    It is described as I2C bus "stall" at the next received byte when this problem occurs.

    So, I think I2C status become Bus Busy while this I2C bus Stall. Is this correct?

    Or CPU freezes when the CPU access the I2C register?

     

    Best Regards,

    Taka

  • Hello Taka-san,

    The Busy Bit during I2C operations is set when a START condition is seen and is cleared after a STOP condition is detected. So if you were to have a bus stall between these, the Busy Bit should still be set. 

    The CPU is not "frozen" when this errata occurs. Rather, the internal state machine within the eUSCI missed the internal RXRead Flag that signals when the RXBUFF has been read. This is why a second read of RX Buff is a workaround.

    Hope this helps!

    Regards,

    JH

  • Hi JH-san

    Thank you very much for your advice. That has become a great help!

    Sincerely,

    Taka

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