I am checking my clocks on my MSP-TS430RGC64C demo board and using the below code to setup the clocks. I have a 32.768 crystal on Xin,Xout. I have the ACLK coming out on a port pin and the MCLK coming out a port pin. The ACLK shows the crystal and the MCLK shows the DCO output.
The ACLK shows a clean 32.768 KHz signal as it should. The MCLK pin is showing a 4.66MHz clock when it should be 4.9152MHz. I tried increasing the FLLD_1 + 149 but the frequency is still 4.66MHz. I also tried changing the DCORSEL_3 to other ranges. Still I get the wrong frequency. Can you help me pinpoint my error.
Also with some settings the MCLK has a lot of jitter.
void ConfigClocksUsingXT1andPLL( void )
{
//turn off XT2;
UCSCTL6 |= XT2OFF;
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap = 12pF
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
}while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag
// Initialize DCO to 2.45MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 |= DISMOD_L;
UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz
UCSCTL2 |= FLLD_1 + 149; // (N + 1) * FLLRef = Fdco
// (149 + 1) * 32768 = 4.9152MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 4.9152MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle
__delay_cycles(153600);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
}
