Gap between the TX bytes in SPI MSP432

Hi All,
some addition to my post: because I am trying to implement I2S protocol I cannot actually keep this gaps. my 32 bits of data should be exactly 1.536 Mhz / 32 = 48 kHz.
Regards,
Andrei

Which interrupts do you use? Rx or Tx? You could also try using the DMA that runs in the background and feeds the USCI module only causing an interrupt when everything is transmitted.

Dennis

Hi Dennis,
I use UCTXIE. And some correction to my previous post: SPI clock 3.072 MHz, I should transmit 64 bit to fit exactly one period with 48 kHz. This is the reason this gap unacceptable. Not I get around 2.5 uS between the bytes. Is this possible to implement with TI chip or better to change it to ST, for example?
Kind regards,
Andrei

Andrei,

UCTXIE is no interrupt flag, but I suspect you are using the TXIFG in that case. I would give the DMA a try.

I think you may be able to send seemingly uninterrupted bytes at ~3Mhz by setting your clocks as follows:

   /*Configure the SMCLK clock to be sourced from the DCO*/
	MAP_CS_setDCOFrequency(48000000);
    MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8);
    MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);

I have similar settings and are able to send bytes with no significant gaps in between. Hope it helps.