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MSP430F5529 ADC configuration

Other Parts Discussed in Thread: MSP430F5529

Hi,

    I am currently working with MSP430F5529 and trying to configure ADC. I am only able to configure A0 channel P6.0 and able to read the result in ADC12MEM0. Whereas when I configure A1 channel P6.1 to read result from ADC12MEM1 I am geting the result in ADC12MEM0. I have not made any configurations for memory register 0 ADC12MEM0, but still I am able to read values from ADC12MEM0.

Kindly refer to the code and tell me if the configurations to read A1 channel using ADC12MEM1 is correct.

#include <msp430.h>

int main(void)
{
WDTCTL = WDTPW + WDTHOLD;                             // Stop WDT
ADC12CTL0 = ADC12SHT0_2 + ADC12ON;          // Sampling time, ADC12 on
ADC12CTL1 = ADC12SHP+ADC12CONSEQ_2; // Use sampling timer
ADC12IE = 0x02;                                                         // Enable interrupt for P6.1
ADC12CTL0 |= ADC12ENC;
ADC12MCTL1= ADC12INCH_1;                           // Enable analog channel 1
P6SEL |= 0x02;                                                        // P6.1 ADC option select
P1DIR |= 0x01;                                                        // P1.0 output
P4DIR= BIT7;                                                           // P4.7 output
while (1)
{
ADC12CTL0 |= ADC12SC;                // Start sampling/conversion

__bis_SR_register(GIE);               //  ADC12_ISR will force exit

}
}

#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
{
switch(__even_in_range(ADC12IV,34))
{
case 0: break; // Vector 0: No interrupt
case 2: break; // Vector 2: ADC overflow
case 4: break; // Vector 4: ADC timing overflow
case 6: // Vector 6: ADC12IFG0
break;
case 8:                                          

// Vector 8: ADC12IFG1
if (ADC12MEM1 >= 700) // ADC12MEM = A1 > 0.5AVcc?
{
P1OUT |= 0x01; // P1.0 = 1
P4OUT = 0x00;
}
else if (ADC12MEM1 <= 700)
{
P4OUT |= BIT7;
P1OUT = 0x00;
}break;


case 10: break; // Vector 10: ADC12IFG2
case 12: break; // Vector 12: ADC12IFG3
case 14: break; // Vector 14: ADC12IFG4
case 16: break; // Vector 16: ADC12IFG5
case 18: break; // Vector 18: ADC12IFG6
case 20: break; // Vector 20: ADC12IFG7
case 22: break; // Vector 22: ADC12IFG8
case 24: break; // Vector 24: ADC12IFG9
case 26: break; // Vector 26: ADC12IFG10
case 28: break; // Vector 28: ADC12IFG11
case 30: break; // Vector 30: ADC12IFG12
case 32: break; // Vector 32: ADC12IFG13
case 34: break; // Vector 34: ADC12IFG14
default: break;
}
}

Thanks in advance

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