configuring DCO

How to configure DCO ( for MSP 430Fg4618)  for SMCLK clock?

  • Hmmm, what do you mean? You do not configure DCO for any clock.

    The DCO is an oscillator. You configure it to oscillate with a frequency. More or less (as the DCO has relatively high tolerances).

    SMCLK is a clock. It is sourced by an oscillator, such as the DCO.

    If you want to know how to configure SMCLK to be sourced by the DCO, then the answer is: It already is at startup. That's the default setting. You can change this by setting the SELS bit in FLL_CTL1. THen SMCLK will be sourced by the (external) XT2 oscillator.

    The frequency of the DCO, however, is controlled by the FN_x bits in SCFI0 register and the DCOx bits in SCFI1. Or automatically adjusted by the FLL hardware, but that's a bit more complex.

    Read the Chapter 5.2 of the MSP430x4xx family users guide SLAU056j.pdf , it explains everything in detail.

     

  • In reply to Jens-Michael Gross:

    Hi,

    Thanks for your reply. But I am still facing a problem. XT2 is not present on my board but a 32.768 KHz watch crystal  connects to Xin & Xout.

    I am configuring DCO for SMCLK clock sourced from the watch crystal.

    Here is my code:

      FLL_CTL0 |= DCOF + DCOPLUS; //DCO oscillator fault condition present, DCO O/P is not divided
      FLL_CTL1 |= XT2OFF;  //Turn off XT2,
      SCFI0 |= FN_2;// f_DCO range = 1.3 to 12.1 MHz
      SCFI0 &= ~FLLD_1;// divide f_DCOLCLK by 1
      SCFQCTL |= 0x1F; //f_DCOCLK = 1.(31 + 1).f_crystal = f_DCOCLK = 32x32.768 kHz = 1.048576 MHz
     
      // Loop until 32kHz crystal stabilizes
      do
      {
          IFG1 &= ~OFIFG;                     // Clear oscillator fault flag
          for ( i=50000; i==0; i--);           // Delay
      }
      while (IFG1 & OFIFG);                   // Test osc fault flag
     
      // disable watchdog
      DisableWatchdog();    // Stop WDT - Password(write - 05Ah) + disable WDT

     

    Problem : When I am setting FLL_CTL1 |= XT2OFF;  //Turn off XT2,system is getting reset always. After commenting it, receiving and sending are still not working.

     

  • In reply to Saurabh Arora:

    Saurabh Arora
    FLL_CTL0 |= DCOF

    DCOF (and the other OF bits) is set if an oscillator fault is detected (and NOT reset automatically). You can only reset it, if you think the fault condition has been removed, and it will reappear after some time (some 100us) if the oscillator is still not oscillating. If you manually set this bit, you tell the clock system that there is no working DCO. MCLK will then switch to XT2 (which isn't there). and then to VLOCLK (LFXT1CLK is not up yet). the WDT is also running on VLOCLK, so the watchdog will reset your system after 32768 VLO clock cycles, long before you disable the watchdog. Also, after setting DCOF, SMCLK will switch from DCO to XT2 as the only available clock source, and then you disable XT2, leaving SMCLK without any clock source.

    You need to disable XT2 (if your device has an XT2 input), or OFIFG will never clear, since XT2OF will be always set.


    Saurabh Arora
    for ( i=50000; i==0; i--);           // Delay

    And once again the classical delay loop. Since I isn't used inside the loop or ever after, any good optimizing compiler will completely eliminate this as dead code.
    If you do something inside the loop that isn't redundant (e.g. writing I into a hardware register that doesn't do anything), the loop will work as expected. As you do now, it will or won't, depending on the used compiler and its optimisation settings.

    Also, you do not set the XCAPxPF bits for the watch crystal capacitors. Do you have external capacitors? If not, the crystal will never come up.