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What is HCLK in MSP432 and Timer32 operation in LPM modes.

Julian Kolodko
Expert 2245 points

G'Day all,

SLAU356A (MSP432 Family Technical Reference) talks about HCLK being used for DMA and for Timer32.

What is HCLK? Its not described in this document or in SLAS826A (MSP432 datasheeet).

How is HCLK related to MCLK  (and FCLK)?  Anything interesting happen in low power modes? Is there any configurability associated with HCLK?

(I notice that table 7-1 says that in some LPM0 states, DMA is limited to 128kHz.  Does that mean that the speed HCLK and therefore Timer32 changes with LPM mode?)

Cheers

Julian

  • 0
    TI__Expert 3295 points
    Julian,

    It seems that you have previously posted a thread very similar to this one that contains most of the answers you are looking for. I have linked the thread below:

    e2e.ti.com/.../1764204

    Please take a look at the answer given by Venu, posted earlier today, for information on how HCLK is related to MCLK and FCLK. Hope this post answers your questions! If you still have questions pertaining to the clocks, I would continue to post in the previous thread to consolidate the information for other community members.

    Best regards,
    Michael Arriete

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