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Problem With SD24 ADC Sampling rate

Other Parts Discussed in Thread: MSP430F6779, MSP430F6779A

Hello,

I am facing some problem with SD24 ADC configuration. I was expected intrrupt at 200uS but it is going in ISR at 220uS. Here is my code

#include <msp430.h>
int main(void)
{
	WDTCTL = WDTPW | WDTHOLD;	// Stop watchdog timer
        P1DIR |= BIT0;
	/***** Unified Clock system ****/
	UCS_config();
        SD24_B_config();
         __delay_cycles(0x3600);                 // Delay for 1.5V REF startup


        SD24BCTL1 |= SD24GRP0SC;                // Set bit to start conversion

        __bis_SR_register( GIE);       // Enter interrupt

}
void UCS_config(void)
{
		PMMCTL0_H = 0xA5;
		PMMCTL0_L = 0x03;
		UCSCTL0 = UCSCTL0 | 0x1F00;
		UCSCTL1 = UCSCTL1 & 0x0000;
		UCSCTL1 = UCSCTL1 | 0x0040;
		UCSCTL2 = UCSCTL2 & 0x0000 ; // FLL Divider
		UCSCTL2 = UCSCTL2 | 0x304F ; // for 20 MHz MCLK and 2.6 MHz SMCLK
		UCSCTL3 = 0x0000;

		UCSCTL4 = UCSCTL4 & 0X0000;
		UCSCTL4 = UCSCTL4 | 0X0043;
}

void SD24_B_config(void)
{
	SD24BCTL0 = SD24REFS | SD24SSEL_1;      // Select internal REF // Select SMCLK as SD24_B clock source

	SD24BOSR0 = 0X0208;		//C7 for 5K samplin; OSR = 520
	SD24BOSR1 = 0X0208;		//C7 for 5K samplin; OSR = 520
	SD24BOSR2 = 0X0208;		//C7 for 5K samplin; OSR = 520
	SD24BOSR3 = 0X0208;		//C7 for 5K samplin; OSR = 520
	SD24BOSR4 = 0X0208;		//C7 for 5K samplin; OSR = 520
	SD24BOSR5 = 0X0208;		//C7 for 5K samplin; OSR = 520
	SD24BOSR6 = 0X0208;		//C7 for 5K samplin; OSR = 520


	SD24BCCTL0 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
	SD24BCCTL1 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
	SD24BCCTL2 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
	SD24BCCTL3 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
	SD24BCCTL4 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
	SD24BCCTL5 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0
	SD24BCCTL6 = SD24ALGN | SD24SCS_4;      // Left-aligned, group 0

        SD24BIE = SD24IE5;
}
__interrupt void SD24BISR(void)
{

// Every 200 uSeconds
	 P1OUT ^= 0x0001;

	if(SD24BIV == SD24BIV_SD24IFG5)
	{
	//	P1OUT = 0x0001;

		Ch0results = SD24BMEMH0 - Ch0_Offset; // Save CH0 higher results (clears IFG)
		Ch4results = SD24BMEMH4 - Ch4_Offset; // Save CH4 higher results (clears IFG)

		Ch1results = SD24BMEMH1 - Ch1_Offset; // Save CH1 higher results (clears IFG)
		Ch5results = SD24BMEMH5 - Ch5_Offset; // Save CH5 higher results (clears IFG)

		Ch2results = SD24BMEMH2 - Ch2_Offset; // Save CH2 higher results (clears IFG)
		Ch6results = SD24BMEMH6 - Ch6_Offset; // Save CH6 higher results (clears IFG)

		Ch3results = SD24BMEMH3 - Ch3_Offset; // Save CH3 higher results (clears IFG)

		

	}
}

I have given output P1.0 to Digital Oscilloscope but it is showing toggling of bit at every 440uS. Which means I am going in my ISR at 220uS. Please let me know where I am making mistake.

Thanks in Advance

Regards

Abhishek

  • First mistake you are doing - not using bit name defines in the code, it is hard to read which bits of UCS and ADC you set so I don't even try.

  • Hello ,

    Thanks for your quick reply,

    I 'll post using bitnames shortly.

    Regards
    Abhishek
  • >I 'll post using bitnames shortly.

    Good. Regarding sample rate: first u shall check that clock runs at expected freq. If possible, configure SMCLK pin for clock output and measure frequency using scope or freq.counter. Then you will know where to look for problem - clock system or ADC

  • Hello

    Your suggesion is absolutely correct. But I have stuck into problem as I was working with MSP430F6779 and this same code was working perfectly
    I was also getting samples at 200uS and my M-clock was at 20.90Mhz.
    When I have replaced it with MSP430F6779A my sampling rate became 220uS and MClock 19.38 Mhz.
    Please let me know is replacement of IC only powering both from debugger can give me change in clock?

    Thanks in advance

    Regards
    Abhishek
  • So you have not ADC but UCS-related problem. Main difference of debugger versus standalone system is init/reset timing. Debugger usually release CPU from reset when VCC and crystal oscillators are stable. Your circuit can fail in this regard. First thing you can try: introduce let's say >-100ms delay after you disable WDT. Also I see that you don't use recommended clock subsystem initialization, at least I do not see any clock error handling.

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