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MSP430F5438(A) - Maximum allowed SPI clock speed

Nikolaos Agianniotis
Intellectual 290 points
Other Parts Discussed in Thread: MSP430F5438A

Hi,

I am using the MSP430F5438A device as an SPI master to drive and read conversion results from an external high-speed ADC.  The desired SPI clock speed for the conversion is 16MHz, in order to achieve conversion throughput of 1MSPS. Do you think that this can be achieved with the microcontroller running at 16MHz or 20MHz clock? According to the datasheet of the device, on page 57, this cannot be achieved. Note1 puts a limit of the SPI output clock to around 8MHz max. Can you please advise me with this case?

Thank you very much for your support.

  • 0
    Guru 227245 points

    Well, I had no problems with an external loop and 16MHz SPI clock on my 5438. I haven't attached a real SD card yet. Of course if the slave is too slow, the maximum usable clock frequency might be limited. If the slave isn't slower than the MSP, even 25MHz should be within the possible range. Depending on your Vcc and core voltage, of course. YOu cannot have high speed and low power. Also, the output timing depends on the attached capacitance. If you can keep it low, Tvalid,mo might greatly decrease.

     

  • 0
    Guru 12160 points

    With the right peripheral, you can go up to 25MHz SPI on the '5438A.

    "Note 1" is a little bit misleading.  In the world of high-speed SPI, peripherals often use only the latching edge of the clock.  They hold outgoing data for a few ns and then autonomously change to the next bit without waiting for the opposite edge on the clock to tell them to change to the next bit.  So the "Tvalid,so" parameter mentioned in the MSP430 documentation is usually negative -- the data from the slave is valid before the clock edge that tells the slave to change to the next bit.  So the "sum" of this negative number and the MSP430 "Tsu,mi" value is smaller than "Tsu,mi".  This reduction in turn brings "Tlo/hi" down too and allows you to get up to 25MHz SPI. 

    You'll need to read the ADC data sheet carefully enough to know which clock edge induces the output change.  For high-speed ADCs, it is usually the latching edge (after some hold time).  In that case, you can subtract 31ns (half a cycle at 16MHz) to get "Tvalid,so" for the MSP430 calculation.  It will be a negative number.  (If not, it can't keep up.)

    Also be sure PMMCOREV = 2 or 3 because you're trying to go faster than 12MHz.

    Jeff

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