msp430f2132 adc10-bit conversion

Praveen,
Can you post your ADC register settings and a screen capture of the scope?

I may have to investigate this and get back to you.

Hello Sir Thanks for replaying, Below are the register configuration for ADC10

ADC10CTL0 = SREF_0 | ADC10SHT_0 | REFON;
ADC10CTL1 = 0x0000; // channel 0
ADC10AE0 = 0x01;

ADC10CTL0 |= ADC10ON;
ADC10CTL0 |= ENC;

for ( ; ; ) {
result = 0;
P2OUT |= 0x10;

ADC10CTL0 |= ADC10SC;

while ( ADC10CTL1 & ADC10BUSY )
;

P2OUT &= ~0x10;

result = ADC10MEM;
ADC10CTL1 &= ~ADC10BUSY;

printf ( "%u\n", result );
}

Sir i forgot to attach the captured wave form

Regards

Praveen

According to the ADC10 Timing Parameters table (SLAS578J, p. 45), ADC10OSC may vary over 3.7-6.3MHz, which my calculator says is +/-25%. A +8% discrepancy wouldn't be very surprising.

It appears (p. 3) that you can put ADC10CLK out on P1.0, which would tell you whether this is the cause.

Hello Sir Can you send the SLAU578j pdf, i tried to download but i could not able to get it.

Regards

Praveen B

SLAS578

It is the datasheet of the MSP430F2132.

Dennis

Hello sir had you check the waveform and register configuration of adc.

Regards

Praveen B

Hello sir good morning, i had observed the readings, i selected adc10osc as adc10clk for adc10 and i checked the timing of one clock it is showing is 5MHz, according to SLAU144J page no 538 and 540 adc takes 13 clock cycles for conversion i.e 13/5MHz ( 2.6 micro sec) only for conversion, in SLAS578J in p.45 for 3.7MHz ( 13/3.7MHz = 3.51 micro sec ) and 6.3MHz ( 13/6.3 = 2.06 micro sec) they given correct calculation, so for 1 adc count it should take 17.5 clock cycle of adc10clk(for 4SHT), in my reading it taking 16.5 clock cycles i do not know on which step i mean in conversion or in sampling losing a one clock, i wanted to attach the wave form of adc10 but i am not finding the option on replay tag.

Regards
Praveen B

Use rich formatting that appears after pressing on reply.

Keep in mind that the code you posted isn't measuring only [ADC time], but actually [ADC time + part of a loop + two halves of setting a port pin]. At a guess, that could be 10+ CPU clocks, and it would be difficult to know exactly without looking at the assembly code. With the precision you seek, one instruction could make a big difference.

How are you correcting for this extra code?

Sir i got what you want to explain, but i am using internal adc10ckl advantage of using this clk is it provide clk ones adc get starts sample and convert after completing it will not provide ckl( SLAU144j page no 537 22.2.4 section), for every conversion it taking one less clock cycles, we can probe adc10clk on cro.

Thanks

Praveen

I don't have an F2132 to work with, but I did try your settings on a G2553 (Launchpad). The G2553 has nominally the same ADC10 unit as the F2132, though I can't say whether the internals are the same.

I count 17 (full) cycles of ADC10CLK for each round.

You quoted Tsync as 0.5 clocks, but I don't see a specification anywhere for that. I expect Tsync can be anything in the interval [0,1), based on phase difference between the SHI clock and the ADC10CLK. Since the ADC10OSC is started by the ADC itself, it seems not unlikely that when ADC10CLK=ADC10OSC, there is no phase difference and Tsync is always 0.

Were you able to upload your waveform capture? I don't see it in your posts.

Sir I attached the wave form please find it, and Timing of ADC10 is explained in MSP430 family user guide(Page no 538 SLAU144J – December 2004 – Revised July 2013), in my wave form also i observed it stating from falling edge of ADC10CLK it exactly matching user guide it means Tsync is 0.5 ADC10CLK and Tsample is depend upon the user configuration (4, 8, 16, 64 ) in my code i selected 4 SHT and Tconvert is 13 ADC10CLK the total clock for one conversion is 17.5 ( Tsync + Tsample + Tconvert = 17.5 if ADC10CLK = 5MHz it should take 3.5 micorsec.

Regards and Thanks

Praveen

Can you post wave form what you tested, and in my board we are using F2132 i replaced with F1232 board did not support, how you are testing the G2553 ic's ?, The user manual SLAU144j is support MSP430X2XX G2553 and F2132 both for same user manual.

Regards and thanks

Praveen B

Unfortunately I can't post my waveform since it was done on a (borrowed) analog scope from which it is difficult to capture (anyone got some 3.5" diskettes?).

I also noticed that the clock signal (P1.3 in my case) idles high, but I don't think that means it exactly matches Figure 22-3. For one thing, Figure 22-3 shows the clock running before SHI, but SHI (ADC10SC) is what starts ADC10OSC. I expect it was drawn that way to allow for e.g. ADC10CLK=SMCLK, where one would expect some phase difference (Tsync>0, but not necessarily 0.5).

At this point I'm at the limit of my visibility into the ADC10, and I don't have an F2132 to work with. If you're seeing 16 (full) ADC10CLKs, rather than 17, to do a conversion, you'll probably have to ask your TI representative.

Praveen,
Does this satisfy your question?

Yes sir, What you explained about tsync , it helped me to get out of my problem.
Thank you
Praveen