MSP430F5659 DCO

Have you configured MSP so to output SMCLK on the corresponding pin?
As per p.92 of datasheet , you have to set DIR and SEL bit and clear LCDS27 bit (the latter is default after reset) of P3.4 as follows:
P3DIR |= BIT4; P3SEL |= BIT4;
Regards,
Peppe

Hello Manish,

First you need to clock out SMCLK on P3.4 by setting P3DIR and P3SEL Bit4. Please check below code, it should give you 16MHz output on P3.4.

This reference code assuming there is 3.3V on VCC and Core is running at Level 3. If not you must check VCC of device using SVS and set PMM core to 3 before setting clock frequency 16MHz. Please go through Power management module and SVS chapter in user guide for more details.

WDTCTL = WDTPW+WDTHOLD;                   // Stop WDT
  P1DIR |= BIT1;                            // P1.1 output

  P1DIR |= BIT0;                            // ACLK set out to pins
  P1SEL |= BIT0;                            
  P3DIR |= BIT4;                            // SMCLK set out to pins
  P3SEL |= BIT4;                            
 
  UCSCTL3 = SELREF_2;                       // Set DCO FLL reference = REFO
  UCSCTL4 |= SELA_2;                        // Set ACLK = REFO
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx

  // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
    
  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL1 = DCORSEL_7;                      // Select DCO range 16MHz operation
  UCSCTL2 |= 511;                           // Set DCO Multiplier for 8MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (511 + 1) * 32768 = 16777216Hz
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
  __delay_cycles(500000);
    
  while(1)
  {
    P1OUT ^= BIT0;                          // Toggle P1.0
    __delay_cycles(600000);                 // Delay
  }

Regards,

Vikas Chola

It seems to me that you do not realize that the effect of "|=" is different from that of "=".

For example, if the original of UCSCTL4 is (SELM_4+SELS_4), then after your:

UCSCTL4 |= SELM_3+SELS_3;

the value of UCSCTL4 will become (SELM_7+SELS_7). Is that what you expect?