ESI signal observation on FR6989 ESI module.

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//******************************************************************************
//
//                     MSP430FR6989
//                  -----------------
//            RST -|             P9.1|--> DAC_output_voltage
//                 |                 |
//                 |                 |
//                 |                 |
//                -|LFIN             |
//     32KHz XTAL  |                 |
//                -|LFOUT            |
//                 |                 |
//
//******************************************************************************
#include <msp430.h>

void ESI_init(void);
void gpio_config(void);
void clk_init(void);

int main(void)
{
	unsigned int i;

    WDTCTL = WDTPW | WDTHOLD;

    gpio_config();
    clk_init();
    ESI_init();

    while(1)
    {
    	// Increases DAC voltage by ~ ((0.8*Vcc)/2^8)
    	// DAC voltage range Vss - (0.8*Vcc)
    	for(i=0;i<0x1000;i+=0x10)
    	{
    		ESIDAC1R0 = i;
    		_delay_cycles(8000000);
    	}
    }

}

void gpio_config(void)
{
	// Configure P9.4 and P9.5 as input pin in ESICH0 and ESICH1 mode
	P9SEL1 |= BIT1;

	// Configure PJ.4 and PJ.5 for 32kHz crystal on LFXT
	PJSEL0 = BIT4 | BIT5;

	// Disable the GPIO power-on default high-impedance mode to activate
	// previously configured port settings
	PM5CTL0 &= ~LOCKLPM5;

}



void clk_init(void)
{
    // Configure Clock System Setup
    CSCTL0_H = CSKEY >> 8;                  // Unlock CS registers
    CSCTL1 = DCOFSEL_6;                     // Set DCO to 8MHz
    // Set SMCLK = MCLK = DCO, and ACLK = LFXT
    CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // Set all dividers to 1
    CSCTL4 &= ~LFXTOFF;

    do
    {
      CSCTL5 &= ~LFXTOFFG;                  // Clear XT1 fault flag
      SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag

    CSCTL0_H = 0;                           // Lock CS registers
}


void ESI_init(void)
{
    // start trigger of ACLK
    ESITSM = ESITSMTRG_1;

    // Timing State Structure initialization
    // TSM State 0 (Idle) configuration
    // In idle mode ACLK is fed to ESI module. Everything is disabled
    ESITSM0 |= (ESICLK + ESISTOP+ ESIDAC);

    // Enable ESI module
    ESICTL |= (ESIEN);

}