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msp432 SPI clock speed

I'm using a msp432p401r chip on the launch pad.

On the front page of the msp432p401r data sheet it says "SPI (up to 16MHz)", page 1.  Later, on page 30, peripheral freq range Vcore0/Vcore1: 12MHz/24MHz., table 5-35, pg 80 says 12MHz/24MHz.

what is the significance of the 16MHz number on page 1?

Also, I want to run one of the eUSCIs in SPI mode as a slave with an external clock (obviously, its a slave).  If using Vcore0, I assume I can clock up to 12 MHz and if I'm using Vcore1 I can clock up to 24MHz.

Is that correct?

thanks

eric

  • Eric,
    I am asking for confirmation, but I believe that the 16Mhz is related to the note 1 found in table 5-38. The f(ucxclk) is actual SPI clock while the f(eusci) is the clock into the peripheral.

    www.ti.com/.../msp432p401r.pdf

    Regards,
    Chris
  • Chris Sterzik said:
    Eric,
    I am asking for confirmation, but I believe that the 16Mhz is related to the note 1 found in table 5-38. The f(ucxclk) is actual SPI clock while the f(eusci) is the clock into the peripheral.

    www.ti.com/.../msp432p401r.pdf

    Regards,
    Chris

    thanks for looking into this.  I looked at table 5-38 and have to say clear as mud.  Not sure why this is so difficult to figure out.  Probably because it depends a how everything is hooked up.

    f_ucxclk = 1/2 t_lo/hi   where t_lo/hi = max(t_valid,mo(eusci) + t_su,si(slave), t_su,mi(eusci) + t_valid,so(slave))

    now assuming we are attaching this master to an on board slave that is the same animal...

    • t_valid,mo(eusci) = 14ns (1.62V)
    • t_su,si(slave) = 3ns
    • t_su,mi(eusci) = 45ns (1.62V)
    • t_valid,so(slave) = 35ns

    t_valid,mo(eusci) + t_su,si(slave) = 17ns,   t_su,mi(eusci) + t_valid,so(slave) = 80ns   so t_lo/hi = 80ns

    I'm pretty sure f_ucxclk should be written as 1/(2 * t_lo/hi) so this yields 1/160ns -> 6.25 MHz.

    If we go with 1/(1/2 t_lo/hi) we get 1/40ns -> 25MHz

    So I'm not at all confident of the f_ucxclk = 1/2 t_lo/hi equation.  That doesn't make sense to me.   f = 1 / t   where t is the period.

    so I'm still not sure where the 16 MHz comes from.

    also on page 83, table 5-39, note (1): It says:

    notice the end of the sentence?  It says see the SPI parameters of the attached slave.  That should be master.

  • Thank you for the feedback. The 16Mhz comes from validation testing done during product development. This test was done between two MSP432 devices. I will continue to work with the team to see if this can be made more clear. Comments are welcome.

    Regards,
    Chris
  • could you also find out the specifics of the test?

    was it done with Vcore1. What was the main processor speed? 32MHz /2 -> SMCLK ->UCxCLK on the master?

    Has any verification testing been done at Vcore0?
  • Eric,
    I mispoke, the 16Mhz was a bench characterization and not a validation test.

    I am still waiting for feedback, but the 16Mhz value is valid for both 32Mhz and 16Mhz operation of MCLK where there SMCLK is derived from this clock. In Vcore = the maximum speed is 12Mhz and therefor the maximum SPI speed would be 12Mhz.

    Regards,
    Chris
  • Chris Sterzik said:
    Eric,
    I mispoke, the 16Mhz was a bench characterization and not a validation test.

    I am still waiting for feedback, but the 16Mhz value is valid for both 32Mhz and 16Mhz operation of MCLK where there SMCLK is derived from this clock. In Vcore = the maximum speed is 12Mhz and therefor the maximum SPI speed would be 12Mhz.

    Regards,
    Chris

    So if I understand. a bench characterization is they ran some kind of test and it worked.  Is that correct?  Do you know what Vcore they were running?  I am assuming Vcore1 so the max peripheral clock can be 24MHz and running SPI at 16 MHz would work.  (at least it did once).

    I don't fully understand: "I am still waiting for feedback, but the 16Mhz value is valid for both 32Mhz and 16Mhz operation of MCLK where there SMCLK is derived from this clock. In Vcore = the maximum speed is 12Mhz and therefor the maximum SPI speed would be 12Mhz."

    It is my understanding that one needs to be at Vcore1 in order to run peripheral clocks faster than 12MHz.  So I don't understand your statement about 16MHz being valid for both 32MHz and 16MHz MCLKs.  I would think that depends on Vcore.  

    If one is at Vcore1 then one can run faster than 12MHz (upto 24MHz) but I haven't seen any verification of faster.

    According to my calculations, at Vcore0 the fastest is something like 6MHz.  And at Vcore1 20MHz.  Using data from table 5-38 and 5-39 in slas826e, msp432p401r datasheet.

    so I'm still not sure what you are trying to tell me.  And still don't understand exactly what the 16MHz means.

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