MSP432P401R: MSP432P401R Status of Errata Fixesv

Hello Ed,
Thanks for asking. That set of errata is actually related to the synchronization of when a flag is set Vs when the flag register is read.
Per the errata, polling the affected flags exacerbates the condition since they will be continually read.
Interrupts reduce the probability of the errata significantly.

To help us understand how this impacts your application, can you tell us more about your system?

How are the 4 UARTs setup? Are you using the LFXT or the DCO to clock the module?
What baud rate is the UART setup for?
Also what is your code base? Are you using direct register access, driver library or TI RTOS?

Regards,
Priya

Hi Priya,

Thanks for addressing my issue.

We are currently using TI's MSP420F5359. and have been using it for several years. We are currently using 4 serial ports even though there are only three on the 5359 by incorporating a mux and a switch.

We have a lot of legacy code, and are addressing a change which will require 6 to 7 uarts in the system as well as SPI. To handle this number of serial ports, we had to bit-bang the SPI.

Because of the additional serial port requirements, we are evaluating using 2 MPU's. We also have the issue of requiring in-field encrypted downloads of  the code. So we have selected at least one of the processors to be the MSP430FP5994 (this also minimizes changes due to a different processor family). The 5994 gives us 4 uarts, as well as a working encrypted download.

Choice of the second processor has to be made. We are evaluating the MSP432P401R vs a second 5994.

All of our code is direct register access. We use a mix of LFXT (32 KHz), and DCO  clock sources depending on serial line baud rate. 

We are not using RTOS.. And we are stuck with a long code sequence in the timer interrupt. Most of our uarts are 9600 baud so we don't miss characters on them. We have one usart at 115KHz, which we control with CTS,

The new project will have interprocessor communication as well as additional uarts with unknown baud rates. Some of these we will not be able to control with CTS.

TI says going to interrupts may reduce the problem, not eliminate the problem.

We only use interrupts, no polling. Because there could be a legacy system on the other side of the line which may be one way, or unable to be controlled by CTS, or unable to buffer or retransmit a message, we have a problem missing characters. 

One option we have is to use DMA to pass messages. Does the errata issue of always getting an interrupt for each character transmitted on a serial line regardless of enabling the interrupt preclude using DMA? 

Should I use a second 5994 or an MSP432, or maybe 2 MSP432's?

Ed,

First I'd like to clarify a few points on the errata.
The latest errata document for Revision C, MSP432P401R has 3 errata pertaining to the UART.
Document link: www.ti.com/.../slaz610h.pdf

I assume USCI44 is the errata you are specifically interested in. So I will keep the discussion focused on it, let me know if this is not the case.

For the UARTs using clocks synchronous (same source) to the CPU, this issue does not exist. Is there any way you can ensure that only synchronous clocks are used? If yes, this will eliminate the issue. I understand that there rare legacy aspects to the system so it may not be possible.

You could use DMA to move the data. However the errata still pertains, since it comes down to the act of reading the UART register with a clock (MCLK/ system clock) that is asynchronous to the Module clock (for example 32kHZ ACLK). I can double check this with our team just to be sure.

In regards to your question of the choice of the second device.
Are these 2 MCUs communication with each other , or only to your 'base' setup?
It's hard to compare the MSP432 to the MSP430FR5994 :) These are different platforms, architecture etc. So it really depends what your sensitivity is in the application - low power, IO count, package, max CPU speed etc to help make the decision.
If the errata is truly the only care about, then it makes sense to use the MSP430FR5994.

Are you using LPM3 in either the F5359 or in the FR5994? Is low power a concern?

-Priya

Hi Priya,

Thanks for your response.
Actually, I was concerned with several errata for the MSP432P401R:
1.TA23 TIMER_A Module
Function Polling timer interrupts may result in a lost interrupt flag
Description Polling any Timer interrupt flag may result in a missed interrupt if the flags are modified
while being read.
Workaround Using an interrupt service routine to service timer interrupt flags significantly reduces the
probability of the issue occurring
We are using interrupts but at 60 Hz, and using it to keep time among other things. We use interrupts, but the system may go for a month or so in the field without ability to adjust. Approximately how how many interrupts do we lose? The amount of lost time is the issue
2. USCI44 eUSCI Module
Function Differing clock sources may cause UART communication failure
Question: Does using a synchronized clock source provide error free communicationfor this issue?
3. USCI46 eUSCI Module
Function UART may receive the first byte incorrectly
Question: Two of the usarts are receiving 9600 baud data. If we use a higher frequency than the 32 KHz and take the hit on power does this provide error free communication for this issue?

We will have two mcus in the system which will communicate with each other. The additional processor is necessary to increase the number of uarts to 6-7. and the second will also handle a color touch screen graphic display.

Ed Ulicki

Ed,

1. What is the clock source for the Timer?

2. Question: Does using a synchronized clock source provide error free communicationfor this issue?

yes, it does. Using the same clock source for eUSCI as the MCLK will solve this issue.

3. Question: Two of the usarts are receiving 9600 baud data. If we use a higher frequency than the 32 KHz and take the hit on power does this provide error free communication for this issue?

yes, it does. What clock source do you plan to use?

-Priya