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MSP430F47167: deactivating XT1, only use DCO and XT2

Part Number: MSP430F47167

Hi @ all!

I'm porting a project from a MSPF2013 to a MSP430F47167 and need MCLK = 8 MHz (or anything above) and SMCLK = 1MHz. With the MSPF2013 this works without external components (crystal), just by the integrated DCO and dividers.

But I haven't found a solution for doing this with the MSP430F47167 without an external crystal.

Any ideas highly welcome!

So I tried it with an additional 16 MHz resonator (value was just laying around) connected to XT2. The idea is to drive MCLK from XT2CLK. And drive SMCLK from FDCO, configured to 1 MHz.

But I can't use XT2CLK as source of MCLK, because I have no crystal on XT1, so it is not working. This causes the LFOF to remain set, which switches MCLK to the DCO, no matter what I set into SELMx.
 I tried to disable XT1    (    __bis_SR_register(OSCOFF);     ), but then the uC stops working completely.

What I'm doing wrong?

Thanks in advance!

  • Hi Peter,

    Please refer to this previous threads:

    e2e.ti.com/.../104603
    e2e.ti.com/.../59210
    e2e.ti.com/.../64597

    You can disable the FLL and modify FN_x and DCOx but the frequency will vary greatly based on temperature and supply voltage. You cannot disable XT1 so as described in Section 5.2.4 of the User's Guide any crystals should be connected to LFXT1, this would require finding a 8 MHz resonator. __bis_SR_register(OSCOFF); puts the MCU in LPM0.

    Regards,
    Ryan
  • OK, than I have to use an oscillator on XT1 as well.

    I added a 3,6 MHz crystal to XT1, the 16 MHz resonator on XT2 is still present. For debugging, the clocks MCLK, ACLK and SMCL are put out on the corresponding pins.

    The test code at the end of this post was used

    I measured the following frequencies:
    ACLK: 3,6 MHz -> OK
    SMCLK: 16 MHz -> OK
    MCLK: 7,2 MHz -> FAILURE, this is still the DCO clock, not XT2 as coded

    Also tried it with

    FLL_CTL1 = SELM_A | SELS;     //MCLK source: XT1, SMCLK source: XT2

    which should output the XT1 clock on MCLK, but there is still the DCO clock.



    I have absolutely no idea what is going wrong




    #include <msp430.h> 
    
    /*
     * main.c
     */
    int main(void) {
        WDTCTL = WDTPW | WDTHOLD;	// Stop watchdog timer
    
        SCFQCTL = 0b00000001;   //N = 1
        SCFI0 = FN_2;           //DCO range control: 001x 2 to 17.9 MHz,
    
        FLL_CTL0 = XTS_FLL;             //LFXT1: High frequency mode
        FLL_CTL1 = SELM_XT2 | SELS;     //MCLK source: XT2, SMCLK source: XT2
        FLL_CTL2 = XT2S_2;              //XT2 range select: 3 to 16-MHz crystal or resonator
    
    
        //output MCLK, SCLK and ACLK for external meassurement
        P1DIR |= BIT1 | BIT4 | BIT5;   //Output: P1.1, P1.4,P1.5
        P1SEL |= BIT1 | BIT4| BIT5;   //special function: P1.1(MCLK), P1.4(SMCLK), P1.5(ACLK)
    
        //infinite loop
        while(1)
        {
            ;
        }
    	return 0;
    }





  • Peter... said:
    MCLK: 7,2 MHz -> FAILURE, this is still the DCO clock, not XT2 as coded

    The posted code is not attempting to clear the crystal oscillator fault bits .

    Section 5.2.11 FLL+ Fail-Safe Operation of the MSP430x4xx Family April 2013 User’s Guide SLAU056L says:

    The OFIFG oscillator-fault interrupt flag is set and latched at POR or when an oscillator fault (LFOF, XT1OF, XT2OF, or DCOF set) is detected. When OFIFG is set, MCLK is sourced from the DCO, and if OFIE is set, the OFIFG requests an NMI interrupt. When the interrupt is granted, the OFIE is reset automatically. The OFIFG flag must be cleared by software. The source of the fault can be identified by checking the individual fault bits.

    When OFIFG is set and MCLK is automatically switched to the DCO, the SELMx bit settings are not changed. This condition must be handled by user software.

    Therefore, I think the OFIFG bit is getting set, during the XT2 startup which leaves MCLK sourced from the DCO as part of the "FLL+ Fail-Safe Operation". When software manages to clear the OFIFG bit, meaning the XT2 oscillator is working, then MCLK should be sourced from XT2.

    See msp430x471x7_hfxt2.c FLL+, MCLK Configured to Operate from XT2 HF XTAL for an example of how to clear the OFIFG bit.

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