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MSP430F6736: PMM15: How to wait for SVSMxCTL settling delay (PMMIFG.SVSMLDLYIFG and PMMIFG.SVSMHDLYIFG) ?

Hideaki Nambu
Mastermind 9125 points
Part Number: MSP430F6736
Other Parts Discussed in Thread: MSP430F6733

Hello,


I would like to implement the PMM15 workaround but the explanation is something confusing to me.
Could you please tell me the code is like?


slaz346 msp430f6733 errata: PMM15:  Workaround:

Any write to the SVSMxCTL register must be followed by a settling delay
(PMMIFG.SVSMLDLYIFG = 0 and PMMIFG.SVSMHDLYIFG = 0) before entering LPM2,
LPM3, LPM4.




Q. I think our code should wait for the values one. Not zeros. Correct ?
  while( !( (PMMIFG & (SVSMHDLYIFG | SVSMLDLYIFG)) == (SVSMHDLYIFG | SVSMLDLYIFG)) ) {}




Q. Before wait, who initializes the bits to zeros ?
   Maybe our code, or the hardware does automatically when the SVMxCTL register is updated ?

p.s. I am aware that slau208, p109 has a reference.  - - void SetVCoreUp()

  • 0
    TI__Guru 56685 points
    Hello Hideaki,

    We are looking into this and will get back to you as soon as possible.
  • 0 in reply to Jace H
    Mastermind 9125 points
    Jace,
    A sooner reply would be highly appreciated. I'm sorry for bothering you.
  • 0
    Guru 244220 points

    The User's Guide says in section 2.2.3:

    If these SVSL and SVML power modes are modified, or if a voltage level is modified, a delay element masks the interrupts and POR sources until the SVSL and SVML circuits have settled. When SVSMLDLYST (delay status) reads zero, the delay has expired. In addition, the SVSMLDLYIFG (SVSL/SVML delay expired) interrupt flag is set. If the SVSMLDLYIE (SVSL and SVML delay expired interrupt enable) is set when this occurs, an interrupt is also generated.

    So you have to wait until the DLYST bits are cleared, or until the DLYIFG bits are set.

    The DLYST bits are set and cleared automatically by the hardware (they are set only during the delay); the DLYIFG bits are cleared by reading SYSNSIV, or by software.

  • 0 in reply to Hideaki Nambu
    TI__Guru 56685 points
    Hello Hideaki,

    Sorry for the delay here as I was trying to get clarification from our designers on the issue. Clemens is correct in that the IFGs are set when the delay is expired and the DLYST bits go to '0' when the delay is over. The DLYST bits actually assert the IFGs by being cleared. The IFG bits are only cleared in Software or accessing the associated ISRs. We are still working out the exact change to the errata text that will amended to reflect this.
  • 0 in reply to Jace H
    Mastermind 9125 points
    Clemens, Jace,
    Thank you for your inputs. Very clear.
    Jace's input was also helpful for understanding.

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