CCS/MSP430FR2033: MSP430FR2033 MCLK not working more than 2MHZ

Hi SHRAVAN BOMMU,

Can you share your test code?

Have you tried FR413x_FR203x CS code example?

//******************************************************************************
//  MSP430FR413x Demo - Configure MCLK for 8MHz sourced from DCO.
//
//  Description: Default DCODIV is MCLK and SMCLK source.
//  By default, FR413x select XT1 as FLL reference.
//  If XT1 is present, the XIN and XOUT pin needs to configure.
//  If XT1 is absent, switch to select REFO as FLL reference automatically.
//  XT1 is considered to be absent in this example.
//  f(DCOCLK) = 2^FLLD * (FLLN+1) * (fFLLREFCLK / n).
//  FLLD = 0, FLLN =243, n=1, DIVM =1, f(DCOCLK) = 2^0 * (243+1)*32768Hz = 8MHz,
//  f(DCODIV) = (243+1)*32768Hz = 8MHz,
//  ACLK = default REFO ~32768Hz, SMCLK = MCLK = f(DCODIV) = 8MHz.
//  Toggle LED to indicate that the program is running.
//
//           MSP430FR4133
//         ---------------
//     /|\|               |
//      | |               |
//      --|RST            |
//        |          P1.0 |---> LED
//        |          P1.4 |---> MCLK  = 8MHz
//        |          P8.0 |---> SMCLK = 8MHz
//        |          P8.1 |---> ACLK  = 32768Hz
//
//
//   William Goh
//   Texas Instruments Inc.
//   March 2014
//   Built with IAR Embedded Workbench v6.10 & Code Composer Studio v6.0
//******************************************************************************
#include <msp430.h>

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop watchdog timer

    __bis_SR_register(SCG0);                // disable FLL
    CSCTL3 |= SELREF__REFOCLK;              // Set REFO as FLL reference source
    CSCTL0 = 0;                             // clear DCO and MOD registers
    CSCTL1 &= ~(DCORSEL_7);                 // Clear DCO frequency select bits first
    CSCTL1 |= DCORSEL_3;                    // Set DCO = 8MHz
    CSCTL2 = FLLD_0 + 243;                  // DCODIV = 8MHz
    __delay_cycles(3);
    __bic_SR_register(SCG0);                // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked


    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                            // default DCODIV as MCLK and SMCLK source

    P1DIR |= BIT0 | BIT4;                   // set MCLK and LED pin as output
    P1SEL0 |= BIT4;                         // set MCLK pin as second function
    P8DIR |= BIT0 | BIT1;                   // set ACLK and SMCLK pin as output
    P8SEL0 |= BIT0 | BIT1;                  // set ACLK and SMCLK pin as second function

    PM5CTL0 &= ~LOCKLPM5;                   // Disable the GPIO power-on default high-impedance mode
                                            // to activate previously configured port settings

    while(1)
    {
        P1OUT ^= BIT0;                      // Toggle P1.0 using exclusive-OR
        __delay_cycles(10000000);           // Delay for 10000000*(1/MCLK)=1.25s
    }
}

BR,

Ling

same code i am using for both the controllers  msp430fr4133 and msp430fr2033

its working fine in 4133

but not working in 2033.