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CCS/MSP432P401R: SPI communication problem

Part Number: MSP432P401R

Tool/software: Code Composer Studio

Hi guys, I have been using the MSP432 for a while now, and first of all I want to thank you all for all the great support you provide here.

Now to my issue, I'm programming the ADS1191 front end. At first, just for the tests, I was using the ACLK as a clock source for the SPI protocol, and it worked just fine. Now I'm trying to use the SMLCK as the clock source, I programmed it at 12 MHz because I need that speed for other peripherials,  and I'm having trouble with the clock divider for the SPI, because I want to make it go at 1 MHz. This is the code I use for the clock.

void configCLK(void){															
	CS->KEY = CS_KEY_VAL;														
	CS->CTL0 = 0x00;														
	CS->CTL0 = CS_CTL0_DCORSEL_4;											
	CS->CTL1 = CS_CTL1_SELA_2 | CS_CTL1_SELM_3 | CS_CTL1_SELS_3 | CS_CTL1_DIVS__2;				
	CS->KEY = 0x00;											
}

And here is the one I use for the SPI protocol.
void configSPI(void){														
    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SWRST; 								
    EUSCI_B0->CTLW0 = EUSCI_B_CTLW0_SWRST | EUSCI_B_CTLW0_MST | 				
            		EUSCI_B_CTLW0_SYNC | EUSCI_B_CTLW0_MSB;              		
    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SSEL__SMCLK; 					
    //EUSCI_B0->BRW = 12;                                                         
    EUSCI_B0->CTLW0 &= ~EUSCI_B_CTLW0_SWRST;						
    EUSCI_B0->IFG &= ~(EUSCI_B_IFG_TXIFG | EUSCI_B_IFG_RXIFG);					
}

As you can see, I commented the BRW instruction, because it doesn't work. When I run my code like this, the communication has no problems, but I'm concerned because the ADS1191 datasheet says that the maximum clock speed is 2 Mhz, that's why I want it at 1 Mhz, but when I put the divider of the BRW register, the communication does't even start. I usually comment my code but I'm from México, so I erased  the comments for easier interpretation.

Thanks, guys.

  • What exactly do you mean with "doesn't work"? No signal? Wrong signal? Wrong frequency?
  • Yeah, no signal at all. The communication does not even start, Clemens.
  • Please show all changes that you made when going from ACLK to SMCLK.
  • I just changed the bit in CTLW0 from:
    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SSEL__ACLK;
    To:
    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SSEL__SMCLK;
    And added the line for the BRW register.
    EUSCI_B0->BRW = 12;
  • How do you determine what happens at the output? Are you using an oscilloscope or logic analyzer?
  • That's right, I have my logic analizer for de CLK, MOSI and MISO.
  • And there's nothing, not even on the CLK line? And 24 MHz works? Did you try other BRW values?
  • Yeah, I've been doing it for a while now and I think I'm getting more confused. This is a picture of my logic analyzer with BRW register with a value of 30, so I'm getting about 390KHz as my clock frecuency.

    And it works, here is one picture with the SMLCK as clock source with no divider in the BRW register, which also works just fine.

    I'm confused because with values lower than 30, I see no signal at all, why it does not work with those values but works at full speed?

  • Andres Zamudio said:

    As you can see, I commented the BRW instruction, because it doesn't work. When I run my code like this, the communication has no problems, but I'm concerned because the ADS1191 datasheet says that the maximum clock speed is 2 Mhz, that's why I want it at 1 Mhz, but when I put the divider of the BRW register, the communication does't even start. I usually comment my code but I'm from México, so I erased  the comments for easier interpretation.

    Thanks, guys.

    I believe the maximum clock speed for the ADS1191 is actually 20 MHz or 15 MHz, depending on DVDD range.

    If your only fear is running it too closely to the maximum speed it allows, you might be safer than you think (correct me if I've misunderstood, but I think your math maybe off by a factor of 10, yes?)

    I will also try to get you an answer to the question about the code, but maybe this makes your issue less concerning (unless my math or understanding is incorrect)?

  • Oh, my bad, I made a mistake there. You are right, and yeah, it might help to get an answer for the code issue but I'm, as you said, less concerned. Thanks a lot!!!
  • Andres,

    I am not sure what the rest of your code is doing, but I am able to use the example code at here and insert the lines from your CS_Config as well as modify the UCB registers and get a 1 MHz clock.

    Here is what my code looks like (these are the only lines I've altered from the example):

    CS->KEY = CS_KEY_VAL;

    CS->CTL0 = 0x00;

    CS->CTL0 = CS_CTL0_DCORSEL_4;

    CS->CTL1 = CS_CTL1_SELA_2 | CS_CTL1_SELM_3 | CS_CTL1_SELS_3 | CS_CTL1_DIVS__2;

    CS->KEY = 0x00;

    P1->OUT &= ~BIT0;

    P1->DIR |= BIT0; // Set P1.0 LED

    P1->SEL0 |= BIT5 | BIT6 | BIT7; // Set P1.5, P1.6, and P1.7 as

    // SPI pins functionality

    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SWRST; // Put eUSCI state machine in reset

    EUSCI_B0->CTLW0 = EUSCI_B_CTLW0_SWRST | // Remain eUSCI state machine in reset

    EUSCI_B_CTLW0_MST | // Set as SPI master

    EUSCI_B_CTLW0_SYNC | // Set as synchronous mode

    // EUSCI_B_CTLW0_CKPL | // Set clock polarity high

    EUSCI_B_CTLW0_MSB; // MSB first

    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SSEL__SMCLK; // ACLK

    EUSCI_B0->BRW = 0x0C; // /2,fBitClock = fBRCLK/(UCBRx+1).

    EUSCI_B0->CTLW0 &= ~EUSCI_B_CTLW0_SWRST;// Initialize USCI state machine

    and here is my output on Logic Analyzer

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