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MSP430F5438A: RTC_A shows strange PS1IFG behaviour

Jürgen Wissenwasser
Intellectual 490 points
Part Number: MSP430F5438A
Other Parts Discussed in Thread: MSP-FET

Hi everybody!

For a low-power-application I utilize RTC_A as interrupt source to wake up the MCU; ACLK=XT1=32768Hz.

The initial code is as follows (MCLK=DCO=12MHz - fast enough):

mov #RT0PSHOLD,&RTCPS0CTL
mov #RT1PSHOLD,&RTCPS1CTL    // Both prescalers are on hold - internal dividers should hopefully be reset (no description about that topic available, by the way)
mov #RT0PSDIV_7,&RTCPS0CTL // CLK-source=ACLK, IRQ not enabled.
mov #RT1SSEL_2+RT1IP_7+RT1PSIE,&RTCPS1CTL
nop
bis #GIE+CPUOFF+SCG0+SCG1,SR // put MCU into LPM3 and wait for interrupt

The point is, that when I set RTCPS1CTL also the IFG is set immediately. This does not only occur in debug mode (IAR Workbench together with latest MSP-FET debugger) but also during runtime. Of cource, under that condition the LPM3 mode is useless and a proper timing is never possible.
The only possibility to override this is to manually reset the IFG before putting the MCU to LPM3, e.g. "bic #RT1PSIFG,&RTCPS1CTL". The crazy thing is that at another code position that problem with a pre-set IFG does not occur.

So, what's the problem with the IFG-flag? And also important: When setting the prescalers on Hold, is its divider also reset?

  • 0
    TI__Genius 15370 points
    Hi Jurgen,

    Do you have a C version of your code to make it a little more human readable? Also, i'd like to test this out on my own setup, can you provide a reduced code version that recreates the issue? At first glance I'm not sure what could be causing the issue, but I'll keep digging. Your code would help immensely though.

    Finally, the dividers are not reset when the prescalers are on hold. By default they are set to 0 (divide by 2) but if you change them and then set the prescaler on hold, they do not return to 0.

    Best regards,
    Caleb Overbay
  • 0 in reply to Caleb Overbay
    Intellectual 490 points
    I did now find out at least one mistake: I increased the SVxL part of the PMM to Full performance but did not set the SVMLE-flag as reported in the errata PMM9.
    If the prescalers are continuously working then it is clear that the IFG can be set too early (especially during debugging) - but the debugger obviously overrides the SVMLE-issue - maybe the delays resulting from JTAG-Communication then override the problem?
  • 0 in reply to Jürgen Wissenwasser
    TI__Genius 15370 points
    Hi Jurgen,

    Thanks for the update. I'm having trouble understanding your last post. Did fixing the PMM bug solve the issue? Can you provide some more clarification?

    Best regards,
    Caleb Overbay
  • 0 in reply to Caleb Overbay
    Intellectual 490 points
    Without setting the SVMLE-Flag the internal 2us-timeout when returning from LPM3 is not enough as the SVxL-comparators require more time - then an erratic SVMLIFG is raised causing a POR - see PMM9.
  • 0 in reply to Jürgen Wissenwasser
    TI__Genius 15370 points
    Hi Jurgen,

    I understand PMM9, but was asking if adding the workaround for this errata helped fix the other RTC issue you were experiencing?

    Best regards,
    Caleb Overbay
  • 0 in reply to Caleb Overbay
    Intellectual 490 points
    I think it now works - of course, when the prescalers never stop operating one never knows when the interrupt really occurs.

    That's my additional question: Is there a possibility to somehow "reset" the prescalers? My intention is to use the RTC as a delay-source in LPM3 without the necessity of continuously reconfiguring a timer. But when I do not know the precise state of the dividers the Interrupts may occur at practically any time.
  • 0 in reply to Jürgen Wissenwasser
    TI__Genius 15370 points
    Hi Jurgen,

    The count value of RT0PS and RT1PS is reset when the RTC module is switched from calendar to counter mode using the RTCMODE bit. You could also write a "0" into the RT0PS and/or the RT1PS register and the write will take effect immediately. This way you can know the precise count when using the dividers as a delay source.

    Best regards,
    Caleb Overbay

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