FROM MY CUSTOMER:
The problem, is we are using a 32kHz crystal for a time base in the clock circuit, divided down to 1 second for timer ticks. Some of the units, not all, exhibit an 8 fold increase in timer operations( i.e. the clock is running 8 times slower than it should).
What the team in Singapore has found is that by increasing the load capacitance on the oscillator the clock can more reliably start. The design parameters seem to be correct for the design, but the errata also suggests increasing the load capacitance to get a more reliable start.
Current design approach: (stray capacitance is the wildcard here)
If we assume 6pf stray, then the correct value for tuning caps would be 13pf
If we assume 2pf stray then the correct value for tuning caps would be 21pf
Increasing the load capacitance on the XTAL has been shown to help fix the issue. There is still more investigation going on to evaluate margin, but it seems that might be a good solution.
In the errata, is suggest not to use both external capacitors and internal capacitors in a design. But the issue is we have many units in the field, and we could update the MCU code and add internal capacitance. Currently there no internal capacitance configured, but we are looking at going to 6pf.
Can you help us understand why both internal and external capacitance might not be recommended?
Any other insight from the MCU team on this errata or other theories of what going on would be helpful?
IF POSSIBLE, I'D LIKE TO ASK IF WE CAN HAVE A CALL WITH THE CUSTOMER TO WALK THROUGH SOLUTIONS.
